Circuit for reducing the transmission delay of the redundancy ev

Details Circuit for reducing the transmission delay of the redundancy ev Circuit for reducing the transmission delay of the redundancy ev

1998-05-11

1999-03-30

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

36523008, 36518905, 365200, 3652257, G11C 800, G11C 700

Patent

active

058897275

ABSTRACT:
The present invention discloses a circuit that reduces the transmission delay of the redundancy evaluation for SDRAM. After an input address is decoded as an external address, the external address is routed to a global factor generator to generate global factors accompanied with an address strobe pulse. The external address is also routed to a redundancy check circuit for starting the redundancy evaluation. Therefore, the redundancy evaluation can be performed as soon as the external address comes. While the external address comes, a column burst pulse and a system clock are directed to the internal counter of the global factor generator for counting continuously. The current count value is treated as an internal address and then routed to the redundancy check circuit to output the ready redundancy evaluation. After the redundancy evaluation and a column synchronous pulse generated by the global column factor generator come to a column redundancy latch, a signal that indicates whether a normal or a redundant memory cell is accessed is sent to a local column factor generator. Finally, a normal or a redundancy bit-line selector is generated to enable a read/write operation. Therefore, the transmission delay that is caused by awaiting the generation of the redundancy evaluation can be significantly reduced.

REFERENCES:
patent: 5625596 (1997-04-01), Uchida
patent: 5717651 (1998-02-01), Kikukawa et al.
patent: 5732030 (1998-03-01), Dorney

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