Circuit for reducing the latch-up sensitivity of a CMOS circuit

Details Circuit for reducing the latch-up sensitivity of a CMOS circuit Circuit for reducing the latch-up sensitivity of a CMOS circuit

1990-06-15

1991-10-08

Jackson, Jr., Jerome

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307313, H01L 2702

Patent

active

050559036

ABSTRACT:
A circuit for reducing the latch-up sensitivity in complementary MOS technology includes a semiconductor substrate of a second conduction type. A first MOS transistor of a first complementary conduction type is disposed in the semiconductor substrate and has a source structure. A well of the first conduction type is disposed in the semiconductor substrate. A second MOS transistor of the second conduction type is disposed in the well and has a source structure. The semiconductor substrate and the source structure of the first transistor are connected to a first supply potential. The well and the source structure of the second transistor are connected to a second supply potential. A third transistor of the first conduction type is disposed in the semiconductor substrate between the first and second transistors. The third transistor has a gate connected to the first supply potential, a drain structure connected to the second supply potential, and a source structure connected to an output.

REFERENCES:
patent: 3636372 (1972-01-01), Hujita et al.
patent: 4021687 (1977-05-01), Yoshimura
patent: 4647956 (1987-03-01), Shrivastava et al.
patent: 4881105 (1989-11-01), Davari et al.
patent: 4922317 (1990-05-01), Mihara
IEEE Transactions on Electron Devices, vol. ED-31, No. 1, Jan. 1984, pp. 62-67; Genda J. Hu: "A Better Understanding of CMOS Latch-Up".
IEEE Circuits and Devices Magazine, H.3, 1988, pp. 8-12; John Y. Chen et al: "Parasitic Effects in CMOS VLSI".
Atlas of IC Technologies: W. Maly: "An Introduction to VLSI Processes", pp. 244-249; The Benjamin/Cummings Publishing Company, Inc.
Dingwall and Stricker: Bulk CMOS Technology; IEEE Journal of Solid State Circuits, vol. SC-12, No. 4, Aug. 4, 1977, pp. 345-348.
R. Troutman: "Latch-Up in CMOS Technology", 1986, pp. 165-196.
R. S. Muller et al: "Device Electronics for Integrated Circuits"; 1986, pp. 458,465.

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