Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Accelerating switching
Reexamination Certificate
1999-12-21
2002-03-26
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Accelerating switching
C327S170000, C327S112000, C327S376000, C327S323000, C326S083000, C326S089000, C326S030000
Reexamination Certificate
active
06362678
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to transistor logic circuits and more specifically to transistor logic circuits used for high speed transistor logic.
Several different logic design technologies are used in implementing circuits, where the particular logic design technology used depends on factors such as speed, power and voltage constraints. One such logic design technology is HSTL (High Speed Transistor Logic). With HSTL, a logical high output (“1” or VOH) is represented by a voltage of about 1.5 volts, while a logical low output (“0” or VOL) is represented by a voltage of about 0.8 volts. In addition, the characteristic impedance, Z
0
, of an HSTL output is usually 50 ohms terminated to 1.5 volts. The rise and fall times for transitions between logical levels are specified to be around 200 to 300 picoseconds (ps).
FIG. 1
shows a typical output driver that might be used to provide an HSTL signal output. The output driver is shown comprising transistors Q
1
, Q
2
, Q
3
, Q
4
, a current source I
1
, a termination resistor RT and a bias resistor R
3
. In operation, Q
1
and Q
2
form a current mirror, with the current source I
1
providing current to Q
1
and a pull-up circuit (Q
4
, RT) providing current to Q
2
. Q
3
and R
3
are provided to correct for beta error in the current mirror.
One problem with the output driver shown in
FIG. 1
is that, if R
3
is large, it will prevent a quick turn off of Q
2
at the beginning of a rising edge of the output. This occurs because, as drive transistor Q
2
is turning off, current from the output leaks to the base of drive transistor Q
2
through the base-collector parasitic capacitance of Q
2
. If R
3
is small, that parasitic current flows through R
3
, but when R
3
is large, that parasitic current ends up being additional base current through Q
2
, thus preventing a quick turn off of Q
2
.
FIG. 2
is a schematic illustrating one solution that has been used to address the above problem. As shown in the schematic, a control transistor Q
5
is coupled between the base of a drive transistor Q
2
and ground. The base voltage of control transistor Q
5
is set by a resistor R
6
, inserted between the base of Q
2
and the base of Q
5
, and by a Shottky diode reverse biased between the base of Q
5
and ground. Another Shottky diode D
3
is provided between the output and the base of Q
5
, to act as a capacitor to turn on Q
5
when the output voltage rises. Alternatively, D
3
could be replaced with a capacitor.
In the circuit shown in
FIG. 2
, D
2
creates a recovery path or clamping action at the base of Q
5
. By the action of D
3
(or a capacitor used in its place), the base of Q
5
rises as voltage at the output rises. This capacitive coupling causes Q
5
to turn on when the output rises, thus helping Q
2
to turn off. That same capacitive coupling causes the base of Q
5
to go negative when the output voltage falls. Without D
2
, the base of Q
5
would go negative enough to reach −VOH+VOL−VBE, or roughly −3 volts. If the base of Q
5
did get that negative, a recovery period would be required to recharge the base of Q
5
, normally through current passed through R
6
. However, with D
2
present, the lower voltage at the base of Q
5
is clamped at −VSBD (about −0.5 volts), so the base of Q
5
recovers faster.
While the circuit shown in
FIG. 2
may shorten the rise time of the output, it is subject to a number of process variations that might be difficult to control, such as the resistance of R
6
, the capacitance of D
3
and the turn-on voltage of Q
5
.
SUMMARY OF THE INVENTION
The present invention provides an improved output driver for HSTL. In one embodiment of an output driver according to the present invention, a bias control transistor is provided to absorb current leaking through the base-collector capacitance of the drive transistor and maintain the base voltage on the drive transistor. The bias control transistor is biased by a series network that urges the bias control transistor to a bias near the bias control transistor's turn-on bias, with a feedback capacitor coupled between the output and the base of the bias control transistor to turn on the bias control transistor when the output rises.
One advantage of the present invention is that it provides a circuit that creates a transient pull-down current for a high speed transistor logic family with controlled characteristic impedance and low level output voltages.
A further understanding of the nature and advantages of the inventions herein may be realized by reference to the remaining portions of the specification and the attached drawings.
REFERENCES:
patent: 4006370 (1977-02-01), Erler
patent: 4159450 (1979-06-01), Hoover
patent: 4593206 (1986-06-01), Neidorff et al.
patent: 4620115 (1986-10-01), Lee et al.
patent: 4682050 (1987-07-01), Beranger et al.
patent: 4855622 (1989-08-01), JohnSon
patent: 4950976 (1990-08-01), Wagoner
patent: 5283480 (1994-02-01), Usami et al.
patent: 5298802 (1994-03-01), Usami et al.
patent: 6100742 (2000-08-01), Erckert
Bosnyak Robert J.
Cruz Jose M.
Cunningham Terry D.
Nguyen Long
Sun Microsystems Inc.
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