Circuit for reducing errors in a data receiver

Details Circuit for reducing errors in a data receiver Circuit for reducing errors in a data receiver

1983-06-30

1985-07-16

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

333 18, 375 99, H03H 736

Patent

active

045301042

ABSTRACT:
In a data receiver, a complex data signal after demodulation and sampling is applied to an equalizer which provides an improved signal which is applied to a phase and amplitude correction circuit for correction utilizing a complex reference vector. The corrected signal is applied to a decision circuit the input and output of which are applied to a difference determinator circuit, the output of which is a complex residual error signal utilized in conjunction with a plurality of gain factors generated in a gain factors generator to determine the reference vector. The gain factors vary in time from transmission initialization such that optimal compensation for transmission disturbances is achieved both at initialization and after stabilization.

REFERENCES:
patent: 3855539 (1974-12-01), Croisier
patent: 3967102 (1976-06-01), McCown
patent: 3972000 (1976-07-01), Desblache et al.
patent: 4091331 (1978-05-01), Kaser et al.
patent: 4253184 (1981-02-01), Gitlin et al.
patent: 4475211 (1984-10-01), Mattis, Jr. et al.

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