Circuit for receiving an AC coupled broadband signal

Wave transmission lines and networks – Coupling networks – With impedance matching

Reexamination Certificate

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Details

C330S304000

Reexamination Certificate

active

06741140

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This is the first application filed for the present invention.
TECHNICAL FIELD
The present invention relates to the field of broadband receivers and, in particular, to circuit for receiving an AC coupled broadband signal.
BACKGROUND OF THE INVENTION
AC (alternating current) coupling of circuits is necessary when interfacing circuits having different bias voltages. AC coupling is typically performed by a DC (direct current) blocking capacitor.
FIG. 1
is a schematic diagram of an example of a circuit
100
with cascading stages, an output stage
102
and a receiving stage
112
, having different operating voltages. The output stage
102
operates between a ground reference
104
and a negative supply
106
; the receiving stage
112
operates between a positive voltage supply
114
and a ground reference
116
. Hence, an output
108
of the output stage
102
will be incompatible with an input
118
of the receiving stage
112
unless a DC blocking capacitor
110
is inserted between the output
108
of the output stage
102
and the input
118
of the receiving stage.
FIG. 2
is a schematic of an AC circuit
200
equivalent to the circuit
100
shown in FIG.
1
. An equivalent of output stage
202
includes a source impedance
204
, having a value Z
S
, and a voltage source
206
connected in series between an output
210
and a ground reference
207
. An equivalent circuit of the receiving stage
212
includes a termination impedance
214
, having a value Z
T
, connected from an input
216
to a ground reference
215
. In this example the voltage source
206
generates a digital waveform
208
such as an NRZ (non-return to zero) or RZ (return to zero) bit stream. A simple rectangular wave
208
is shown for convenience in this example. A resulting waveform
218
at the input
216
to the receiving stage
212
has voltage spikes and distortion due to a differentiating effect of the blocking capacitor
110
.
Those voltage spikes can damage an amplifier's input stage resulting in either immediate failure or early life failures. This problem is more acute when using high supply voltages in the order of 10 to 12 V instead of more typical 7 to 8 V, for example, in multi-chip modules, interfacing two modules from different suppliers or interfacing RF (radio frequency) drivers to electro-optical modulators, especially crystal-cut Lithium Niobate high speed electro-optical modulators which require high drive voltages.
The problem is more severe when long runs of consecutive ones and zeroes occur in the digital waveform
208
. In SONET (synchronous optical network) systems, SONET scrambling algorithms take care of this to some extent but some operating conditions such as start-up or test conditions may nevertheless result in long runs of ones or zeros.
Another possible solution is diode clamps consisting of stacks of diodes to snub out spikes. This is usually not sufficient and a disadvantage is that they distort the waveform.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a receiving circuit that overcomes the problems and disadvantages of the prior art stated above.
In accordance with the invention there is provided a receiving circuit that includes a termination impedance and an equalization capacitor. The value of the equalization capacitor is chosen such that voltage spikes and distortion on a received signal are significantly reduced.
In accordance with another aspect of the invention there is provided a distributed electronic amplifier having a receiving circuit that includes a termination impedance and an equalization capacitor. The value of the equalization capacitor is chosen such that voltage spikes and distortion on a received signal are substantially reduced.
In accordance with still another aspect of the invention there is provided an electro-optic modulator having a receiving circuit that includes a termination impedance and an equalization capacitor. The value of the equalization capacitor is chosen such that voltage spikes and distortion on a received signal are substantially reduced.


REFERENCES:
patent: 4713563 (1987-12-01), Marshall et al.
patent: 4978872 (1990-12-01), Morse et al.
patent: 5301081 (1994-04-01), Podell et al.
patent: 5339047 (1994-08-01), Mizan et al.
patent: 5424691 (1995-06-01), Sadinsky
patent: 5463359 (1995-10-01), Heaton
patent: 5650908 (1997-07-01), Stanton
patent: 5969582 (1999-10-01), Boesch et al.
patent: 6243566 (2001-06-01), Peckham et al.
patent: 6414562 (2002-07-01), Bouisse et al.
TriQuint Semiconductor Product Data Sheet “DC—14 GHz Power Amplifier”, Texas USA, Mar. 23, 2001.

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