Circuit for reading non-volatile memories

Details Circuit for reading non-volatile memories Circuit for reading non-volatile memories

1996-07-31

1998-03-31

Nguyen, Viet Q.

Static information storage and retrieval

Floating gate

Particular biasing

36518524, 36518901, 365191, G11C 1606

Patent

active

057346100

ABSTRACT:
A reading circuit includes, for each bit line of a matrix of memory cells, a controllable switching element which can connect the bit line to a voltage source in response to a control signal applied to a control terminal thereof, a detector stage sensitive to the flow of current through the bit line, and a driving stage including two field-effect transistors connected in the inverter configuration with the input of the inverter connected to the bit line and with the output of the inverter connected to the control terminal of the controllable switching element. In order to charge the capacitance associated with the bit line rapidly but without causing oscillatory phenomena, the driving stage includes circuitry for reducing the gain of the feedback loop formed by the inverter and by the controllable switching element.

REFERENCES:
patent: 5175705 (1992-12-01), Iwahashi
patent: 5303189 (1994-04-01), Devin et al.
patent: 5608687 (1997-03-01), Komarek et al.
European Search Report relating to EP 95 83 0357, filed on Aug. 4, 1995.
Patent Abstract of Japan, vol. 17, No. 585 (P-1632), Oct. 25, 1993 & JP-1A-05 166389, Jul. 2, 1993.

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