Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2010-11-24
2011-12-20
Sofocleous, Alexander (Department: 2824)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S051000, C365S149000, C365S230030, C365S233130, C711S105000, C711S115000
Reexamination Certificate
active
08081535
ABSTRACT:
A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated by a first number of chip-select signals. The circuit is configurable to receive bank address signals, a second number of chip-select signals, and row/column address signals from the computer system. The circuit is further configurable to generate phase-locked clock signals in response to clock signals received from the computer system and to provide the first number of chip-select signals to the first number of ranks in response to the phase-locked clock signals, the received bank address signals, the received second number of chip-select signals, and at least one of the received row/column address signals.
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U.S. Appl. No. 12/815,339, filed Jun. 14, 2010; Owned by Netlist, Inc.
U.S. Appl. No.
Bhakta Jayesh R.
Solomon Jeffrey C.
Knobbe Martens Olson & Bear LLP
Netlist, Inc.
Sofocleous Alexander
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