Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2000-04-03
2002-06-04
Sherry, Michael J. (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C361S091500, C330S20700P
Reexamination Certificate
active
06400541
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to circuitry for protection of sensitive circuitry against electrostatic discharge and, more particularly, to protection circuits for protection of differential inputs, such as differential RF inputs.
BACKGROUND OF THE INVENTION
The inputs to semiconductor circuits are vulnerable to damage or destruction by electrostatic discharge (ESD). Although protection circuits have been utilized in the prior art, the protection of radio frequency (RF) circuits against electrostatic discharge is particularly difficult. Protection circuits may involve the connection of diodes between the RF inputs and ground. The diodes are biased into conduction by an electrostatic discharge and thereby prevent the application of high voltages to the sensitive RF circuit. Such RF inputs may be connected to the front end of a low noise receiver for receiving very low level signals, and capacitance added by the protection circuit degrades RF performance. An example of such an RF circuit is the receiver in a mobile telephone. Thus, the challenge in developing protection circuits for RF circuitry is to provide adequate protection against electrostatic discharge without producing an unacceptable degradation in performance.
One prior art protection circuit is shown in
FIG. 5. A
differential amplifier includes bipolar transistors
10
,
12
and
14
. Differential inputs IP and IPB are connected to the bases of transistors
10
and
14
, respectively. A diode
20
is connected between the base and emitter of transistor
10
, and a diode
22
is connected between the base and emitter of transistor
14
. For small signals, node
24
, the common emitter of transistors
10
and
14
, acts as a virtual ground. The base-emitter junctions of transistors
10
and
14
provide a nondestructive discharge path for ESD events, and diodes
20
and
22
provide additional protection against ESD events. This circuit provides limited protection against ESD events involving the supply pins. In addition, its use is limited to circuits which employ bipolar transistors at the inputs.
A widely used prior art protection circuit is shown in FIG.
6
. Diodes
30
-
36
are connected between differential inputs IP and IPB, and diodes
40
-
46
are connected between the differential inputs and the power supply pins VCC and VEE. The protection circuit shown in
FIG. 6
is limited to use with low frequency signals because of the large capacitive loading imposed by diodes
40
-
46
. Reducing the sizes of the diodes
40
-
46
reduces the effectiveness of the ESD protection.
An ESD protection circuit for integrated circuits having a bipolar differential input is disclosed in U.S. Pat. No. 5,862,031 issued Jan. 19, 1999 to Wicker et al.
Because known protection circuits capacitively load RF inputs, RF inputs are often left unprotected and vulnerable to damage. Accordingly, there is a need for improved circuits for protection of differential inputs against electrostatic discharge.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, a circuit is provided for protection of differential inputs of circuitry against electrostatic discharge. The circuit comprises first and second diodes connected in opposite directions between a first differential input pin and a virtual ground node, third and fourth diodes connected in opposite directions between a second differential input pin and the virtual ground node, a first protection device connected between the virtual ground node and a first external pin, and a second protection device connected between the virtual ground node and a second external pin.
The first and second protection devices may comprise fifth and sixth diodes, respectively. In a preferred embodiment, each of the fifth and sixth diodes is larger than each of the first, second, third and fourth diodes. Preferably, the first, second, third and fourth diodes are matched. The first external pin may comprise a positive supply pin, and the second external pin may comprise a negative supply pin or a circuit ground pin.
In one embodiment, each of the first, second, third and fourth diodes is implemented as a collector-base junction of a transistor. In another embodiment, the first diode comprises the base-emitter junction of a first transistor of a differential pair, the third diode comprises a base-emitter junction of a second transistor of the differential pair, and the virtual ground node is a common emitter of the differential pair.
According to another aspect of the invention, a method is provided for protecting differential inputs of circuitry against electrostatic discharge. The method comprises the steps of (a) providing a first discharge path between a first differential input pin and a virtual ground node, (b) providing a second discharge path between a second differential input pin and the virtual ground node, (c) providing a third discharge path between the virtual ground node and a first external pin, and (d) providing a fourth discharge path between the virtual ground node and a second external pin. Preferably, the first and second discharge paths are bidirectional.
According to a further aspect of the invention, a circuit is provided for protection of differential inputs of circuitry against electrostatic discharge. The circuit comprises first and second diodes connected in opposite directions between a first differential input pin and a virtual ground node, third and fourth diodes connected in opposite directions between a second differential input pin and the virtual ground node, and a protection device connected between the virtual ground node and an external pin.
REFERENCES:
patent: 3879640 (1975-04-01), Schade, Jr.
patent: 4044313 (1977-08-01), Wittlinger et al.
patent: 4158863 (1979-06-01), Naylor
patent: 4440980 (1984-04-01), Bakker
patent: 5764464 (1998-06-01), Botker et al.
patent: 5862031 (1999-01-01), Wicker et al.
patent: 5905617 (1999-05-01), Kawasoe
patent: 0 631 318 (1994-12-01), None
patent: 2 008 357 (1979-05-01), None
patent: 02 246613 (1990-10-01), None
Analog Devices Inc.
Sherry Michael J.
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