Static information storage and retrieval – Read only systems – Fusible
Reexamination Certificate
2002-06-24
2003-12-09
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read only systems
Fusible
C365S225700
Reexamination Certificate
active
06661693
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuit memory products, and, more particularly, to circuitry for programming antifuse bits in such products.
2. Description of the Prior Art
Contemporary memory products, e.g. DRAMs, require a high degree of redundancy in order to improve manufacturing yields. Present redundancy techniques in such memory products include providing extra memory array columns and/or extra memory array rows which can be used to replace defective columns and/or rows.
One application in which antifuses have been used is as nonvolatile programmable memory elements to store logic states which would be used in DRAMs for row and column redundancy implementation. An antifuse is, by definition, a device which functions as an open circuit until programmed to be a permanent short circuit. Antifuses for redundancy implementation are usually constructed in the same manner as the memory cell capacitors in the DRAM array.
In contemporary memory products, banks of antifuse elements are typically provided, and one such bank is illustrated in FIG.
1
. Each such bank includes a plurality, n, of antifuse elements AF
0
, AF
1
, . . . AF
n
, the top plates of which are joined in a common connection to the programming voltage CGND. The bottom plate of each antifuse element AF
i
is connected to the drain of a protection transistor PT
i
. The source of each protection transistor PT
i
is connected to the drain of selection transistor ST
i
, and the sources of the selection transistors ST
i
are joined in a common connection to ground. The function of each protection transistor PT
i
is to protect the selection transistor from breakdown between its N+ region and gate when the high programming voltage is applied to the drain. The gate of each selection transistor ST
i
is respectively connected to the outputs of NOR gate NG
i
, the inputs of which are the signal PGM* and the selection signals A
i
*. The selection signals A
i
* are the complements of the signals A
i
and may correspond to the address of a row in the memory product which is to be repaired.
A particular antifuse element, e.g. AF
i
, is selected for programming when A
i
* and PGM* are both zero volts. In this condition the output of NG
i
is approximately +5 volts which turns on the selection transistor ST
i
to which it is connected. When this selection occurs, a path exists between the bottom plate of the selected antifuse device and ground. Hence, the selected antifuse device AF
i
sees a large voltage CGND, e.g. 9 to 12 volts, between its top and bottom plates, which is a sufficient voltage to program the antifuse element. When two or more antifuse elements are to be programmed, the same voltage CGND is applied in parallel to the antifuse elements to be programmed.
Several shortcomings exist in utilizing the programming technique for antifuse elements such as shown in FIG.
1
. First, programming of the antifuse elements is slow using the technique shown in
FIG. 1
, because each antifuse element has to be programmed one at a time. This is due to the fact that each antifuse element needs a minimum amount of current and voltage to program correctly. If two antifuse elements are enabled for programming at the same time, one most assuredly will breakdown (i.e., become programmed) before the other. The programmed antifuse thus creates a path to ground for the current from CGND, which may impact the voltage and current needed for programming of the other antifuse element. In other words, the voltage across the slower-to-program antifuse element may be reduced to a level that no programming of this element is realized. Additionally, the problem may become acute when one attempts to program three or four antifuse elements in such a bank at once. Accordingly, the prior art solution to these problems was to program the antifuse elements in a bank one at a time, which results in the speed of redundancy repair of a memory product being reduced.
Once programming of antifuse elements is completed, it is important that the user verify that those elements which are to be programmed are in fact programmed. Also, it is important that the user verify that antifuse elements which are not to be programmed are functioning properly. In the latter regard, unprogrammed antifuse devices may leak and appear to be programmed devices. No such verification circuitry has heretofore been available.
SUMMARY OF THE INVENTION
In accordance with the present invention, improved circuitry is provided for programming antifuse devices. With the present invention, the speed of programming antifuse elements is enhanced, because all of the antifuse elements in a bank may be programmed simultaneously.
In one embodiment of the present invention, the same programming voltage CGND is still applied in parallel across all antifuse elements to be programmed by enabling this respective selection transistors. However, in this embodiment, a feedback circuit is associated with each antifuse element to stop the flow of current from CGND through the antifuse element once it is programmed. With this feedback circuitry, a programmed antifuse element can no longer affect the voltage across and current through antifuse elements which are slower to program.
In another embodiment of the present invention, circuitry is provided which generates a separate programming voltage pulse for each antifuse element in a bank which is selected for programming. In this embodiment, the same voltage source is not applied in parallel across all of the antifuse elements that are to be programmed, and the programming voltage across and current through an antifuse element that is to be programmed is unaffected by other antifuse elements which may have programmed more quickly.
In accordance with the present invention, method and apparatus are provided to verify that an antifuse element is programmed properly. The method and apparatus also verify if a nonprogrammed antifuse element is functioning properly.
REFERENCES:
patent: 5495436 (1996-02-01), Callahan
patent: 5706238 (1998-01-01), Cutter et al.
patent: 6011742 (2000-01-01), Zheng
patent: 6055173 (2000-04-01), Mullarkey et al.
patent: 6130834 (2000-10-01), Mullarkey et al.
patent: 6424584 (2002-07-01), Seyyedy
patent: 6445605 (2002-09-01), Mullarkey et al.
patent: 6477094 (2002-11-01), Kim et al.
Graalum Jason
Habersetzer Daryl L.
Kurth Casey R.
Mullarkey Patrick J.
Browning & Bushman P.C.
Elms Richard
Kress Hugh R.
Micron Technology
Nguyen Hien N.
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