Static information storage and retrieval – Floating gate – Particular biasing
Patent
1998-08-27
2000-01-11
Nelms, David
Static information storage and retrieval
Floating gate
Particular biasing
36518523, G11C 1606
Patent
active
060143312
ABSTRACT:
The circuitry for programming a flash EEPROM memory cell has a data import circuit for receiving a data signal and a programming signal. Switching circuit is coupled with the data input circuit and responsive to the programming signal for transmitting the data signal to achieve the memory cell from the output of the data input circuit. Discharge control circuit, is coupled with the switch circuit for discharging the bit line voltage of the memory cell. The discharge control circuit comprises two NMOS transistor and a PMOS transistor. First one of the NMOS is coupled with a PMOS in a series so as to construct a shunt circuit for discharging the bit line voltage and the PMOS is then coupled with the second NMOS in a parallel way. The gate terminal of PMOS is then responsive to ground voltage, the gate terminals of two NMOS are then responsive to a voltage V.sub.PBIAS. Decoder circuit is coupled with the switch circuit, for addressing the memory cell, wherein the decoder is under controlled by at least one transistor.
REFERENCES:
patent: 5008856 (1991-04-01), Iwahashi
patent: 5268886 (1993-12-01), Momodomi et al.
patent: 5532964 (1996-07-01), Cernea et al.
patent: 5777945 (1998-07-01), Sim et al.
Ho Hoai V.
Nelms David
Novick Harold L.
Taiwan Semiconductor Manufacturing Co. Ltd.
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