Circuit for producing a polarity-reversed voltage with opposite

Details Circuit for producing a polarity-reversed voltage with opposite Circuit for producing a polarity-reversed voltage with opposite

1978-10-02

1981-03-31

Edlow, Martin H.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307255, 307304, 307583, H03K 500

Patent

active

042596866

ABSTRACT:
An inverter is controlled by first clock pulses for converting a positive power supply into second clock pulses having a first voltage level of the power supply and a second voltage level of a reference voltage. The second clock pulses are supplied to a capacitor. The source-drain path of a first impedance varying P-FET is connected between the output terminal of the capacitor and the reference voltage and is controlled so as to take a low impedance when the second clock pulses are at the first voltage level while a high impedance when the second clock pulses are at the second voltage level. The source-drain path of a second impedance varying P-FET is connected between the output terminal and a terminal for taking out a polarity-reversed voltage. The second impedance varying P-FET is supplied at the gate with the first clock pulses so as to be controlled to take a high impendance when the second clock pulses are at the first voltage level and a low impedance when the second clock pulses are at the second level.

REFERENCES:
patent: 3651342 (1972-03-01), Dingwall
patent: 4142114 (1979-02-01), Green
Pashley et al., 1976, IEEE Int. Solid State Circuits Conf. pp. 138-139.
Electronics Review, Sep. 16, 1976, pp. 42-43.
Frantz et al., I.B.M. Tech. Discl. Bull., vol. 11, No. 10, Mar. 1969.

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