Pulse or digital communications – Systems using alternating or pulsating current
Reexamination Certificate
2000-05-26
2002-12-24
Pham, Chi (Department: 2631)
Pulse or digital communications
Systems using alternating or pulsating current
Reexamination Certificate
active
06498817
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a circuit arrangement which includes a stage for the processing of data signals which are applied to the stage in a selectable sequence during time intervals which are defined by a clock signal.
2. Description of the Related Art
Circuit arrangements of this kind are used in a wide variety of digital switching circuits which process data. Notably when such circuit arrangements, or their elements, are constructed while using CMOS circuits their current consumption can be strongly reduced, because such CMOS circuits, and gates constructed using such circuits, consume current only when value of the data signals occurring therein changes. Consequently, the current consumption of a circuit arrangement thus constructed is dependent on the changes of the data signals. This could make it possible to extract information as regards the changes of the data, and hence as regards the data themselves, from the variation in time of the current consumption. Such information, however, should not be surrendered, notably not in the case of data signals which are to be kept secret.
This problem becomes acute when parts of synchronously operating logic circuits are clocked only conditionally in order to save current, i.e. only when the relevant circuit element is indeed used for the current data signal processing. It is exactly this aim to minimize the current consumption that makes dependencies of the current consumption on the data signals particularly noticeable. Such switching circuits exhibit distinct dependencies of the electrical power consumption on the processed data signals.
SUMMARY OF THE INVENTION
It is an object of the invention to construct a circuit arrangement of the kind set forth in such a manner that the dependency of the power consumption on the data signals is disguised.
This object is achieved in a circuit arrangement of the kind set forth in that in a respective part of each time interval the circuit arrangement is supplied with modified data signals instead of the data signals to be processed.
In accordance with the invention, the described circuit arrangement is thus supplied with other, as different as possible data before processing the actually intended data. It can thus be achieved that the number of switching operations in the circuit arrangement is approximately the same in each time interval, irrespective of whether and how much the data signals to be actually processed change and what values they assume. This results in a power consumption which can no longer be correlated with the processing of the actual data signals.
The invention offers the advantage that the same circuit arrangement is used for the actual task, i.e. for the data signals to be actually processed, as well as for causing an additional current consumption by the processing of modified data signals which have an apparent meaning only. This takes place in a kind of time multiplex in each of the time intervals. More specifically, a dummy operation without meaning and the operation involving the actual data signals to be processed are thus performed sequentially.
When the time intervals are defined, for example by a square-wave clock signal, the modified data signals can be processed in a respective half period of the clock signal and the data signals to be actually processed in the respective other half period of the clock signal. The modified data signals, however, can also be supplied and processed in time intervals which are short in comparison with the period of the clock signal and are situated at the area of, for example the edges of the clock signal, whereas the data signals to be actually processed are supplied during the remaining time intervals of the periods of the clock signal.
The invention achieves a very effective disguise while using very few circuit means. This is realized at the expense of a slightly increased current consumption.
Preferably, the modified data signals are derived from the data signals to be actually processed by means of a data modification device which is controlled by the clock signal and can be simply inserted in the paths for the data signals. Preferably, such a data modification device includes an exclusive-OR circuit or a multiplexer device. A preferred embodiment of the circuit arrangement according to the invention includes a combinatory logic circuit which is inserted in the stage for the processing of the data signals. This combinatory logic circuit may be connected so as to precede the data modification device. The data signals to be processed can be applied from a first storage device to the combinatory logic circuit via the data modification device, the data signals formed in the combinatory logic circuit being applied to a second storage device so as to be stored.
Particularly advantageous is the use of the circuit arrangement according to the invention in combination with CMOS circuits. The application, however, is in principle not restricted to such circuits.
Disguising is achieved notably in that the combinatory logic circuit must process new data signals in each time interval, i.e. in that these data signals change under the influence of the data modification device. This precludes pronounced differences in the power consumption of the circuit arrangement for different time intervals, which differences could arise, for example, when the data signals to be processed contain very few changes only.
REFERENCES:
patent: 4501002 (1985-02-01), Auchterlonie
patent: 4730265 (1988-03-01), Bjornholt
patent: 5117135 (1992-05-01), Lee et al.
patent: 5331669 (1994-07-01), Wang et al.
patent: 5574732 (1996-11-01), Hsieh et al.
patent: 5652536 (1997-07-01), Nookala et al.
patent: 5798661 (1998-08-01), Runaldue et al.
patent: 5867036 (1999-02-01), Rajsuman
patent: 5883529 (1999-03-01), Kumata et al.
patent: 5999086 (1999-12-01), Ecker
patent: 6031396 (2000-02-01), Hoshen et al.
patent: 6127864 (2000-10-01), Mavis et al.
patent: 6151356 (2000-11-01), Spagnoletti et al.
patent: 31212970 (1983-05-01), None
patent: 3324820 (1985-01-01), None
patent: 3623263 (1987-01-01), None
patent: 3539129 (1987-05-01), None
patent: 3942431 (1990-06-01), None
patent: 002020236 (1980-12-01), None
patent: 0089596 (1983-09-01), None
patent: 0164785 (1985-12-01), None
patent: 0390452 (1990-10-01), None
patent: 0390452 (1990-10-01), None
patent: 0396461 (1990-11-01), None
patent: 0658995 (1995-06-01), None
patent: 0716501 (1996-06-01), None
patent: 2062915 (1981-05-01), None
patent: 2089601 (1982-06-01), None
patent: 2209908 (1989-05-01), None
patent: 2233177 (1991-01-01), None
patent: 06311153 (1994-11-01), None
patent: 07038535 (1995-02-01), None
patent: 09284058 (1997-10-01), None
patent: 9107015 (1991-05-01), None
Bayard Emmanuel
Pham Chi
Piotrowski Daniel J.
LandOfFree
Circuit for processing data signals does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit for processing data signals, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit for processing data signals will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2970043