Circuit for prioritizing outputs of an associative memory with p

Details Circuit for prioritizing outputs of an associative memory with p Circuit for prioritizing outputs of an associative memory with p

1992-09-01

1995-05-23

Robertson, David L.

Static information storage and retrieval

Magnetic bubbles

Guide structure

365 49, 36518907, 36523006, G11C 1500

Patent

active

054189233

ABSTRACT:
An encoding circuit shortens time required for a coincidence signal to be converted into an address code after selected and output sequentially according to a predetermined priority level when the coincidence signal is obtained from an associative memory. The circuit is provided with a contention arbitrating circuit for a lower subgroup and a contention arbitrating circuit for a higher subgroup. In the contention arbitrating circuit for a lower subgroup and the contention arbitrating circuit for higher subgroup, each coincidence signal simultaneously activates inhibiting signals whose priority levels are lower than the priority level of the coincidence signal. A lower half of coincidence signals are arranged in descending order in the contention arbitrating circuit for a lower subgroup and a higher half of coincidence signals are arranged in ascending order in the contention arbitrating circuit for a higher subgroup. The contention arbitrating circuit for a lower subgroup and the contention arbitrating circuit for a higher subgroup are arranged in a triangular array and a complementary triangular array, respectively.

REFERENCES:
patent: 3913075 (1975-10-01), Vitalier et al.
patent: 4523301 (1985-06-01), Kadota et al.
"An 8-kbit Content-Addressable and Reentrant Memory", by H. Kadota et al., IEEE Journal of Solid-State Circuits, vol. SC-20, No. 5, Oct. 1985, pp. 951-956.
"An Integrated Content Addressable Memory System", by Jon Patrick Wade, pp. 104-110.
"Content-Addressable Memories", by Teuvo Kohonen, vol. 1, pp. 136-143.

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