Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-07-15
2002-01-01
Hjerpe, Richard (Department: 2774)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S098000, C345S099000, C345S100000, C345S211000, C345S213000, C345S214000
Reexamination Certificate
active
06335715
ABSTRACT:
This application claims the benefit of Korean Patent Application No. 98-47566, filed on Nov. 6, 1998, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly, to a current preventing circuit for a liquid crystal display.
2. Description of the Related Art
A liquid crystal display (LCD) is, among other things, light weight, thin, and consumes low power. The LCD provides a highly enhanced picture quality owing to an improvement in a liquid crystal material and a development in the fine picture element (or pixel) treatment technique. Accordingly, the LCD has a wide range of applications. Such an LCD allows a picture corresponding to image signals to be displayed on a liquid crystal panel by controlling a light quantity passing through the liquid crystal panel based on the image signals. The liquid crystal panel of the LCD comprises a number of liquid crystal cells arranged in a matrix pattern, and a number of control switches such as thin film transistors (TFTs) for switching image signals to be applied to each liquid crystal cell. Further, the LCD includes a gate driver for driving the control switches. The gate driver consists of a plurality of gate drive integrated circuits, hereinafter referred to as “gate D-ICs”.
For example, as shown in
FIG. 1
, the conventional LCD includes 1st to nth gate D-ICs
4
a
-
4
n
for respectively driving gate lines in a liquid crystal panel
6
. A timing controller
2
generates a row drive clock RCLK, a start pulse SP, and an output enable signal OE. The gate D-ICs
4
a
-
4
n
respond to the start pulse from the timing controller
2
sequentially, and respond to the output enable signal OE and the row drive clock RCLK simultaneously. Each gate D-IC is provided with a shift register for shifting the start pulse SP by one bit in response to the row drive clock RCLK, and a level shifter array for level-shifting each logical signal at output channels from the shift register. The level shifter array responds to the output enable signal OE to apply the level-shifted signal to the gate line in the liquid crystal panel
6
as a scanning signal. Accordingly, the gate lines in the liquid crystal panel
6
are sequentially enabled for each horizontal synchronous interval by means of the gate D-ICs.
The gate D-ICs
4
a
-
4
n
generate a rush current at the time of applying an initial power. This results from a reset function of the gate D-IC that is eliminated from the LCD to reduce the size of gate D-IC
4
and an error therein. More specifically, when an initial power is applied to the LCD, logical signals in an unknown state emerge at each output channel of the shift register included in the gate D-ICs
4
. These unknown state logical signals change a high logic into a low logic or vice versa whenever the row drive clock RCLK is applied to the gate D-ICs
4
a
-
4
n
. The unknown state logical signals are not eliminated until a ground logic of start signal is shifted into the last output channel of the last gate D-IC
4
n
. Further, the unknown state logical signals are applied to the gate lines in the liquid crystal panel
6
after being level-shifted with the level shifter array. At this time, specific logic states (e.g., high logic) of the logical signals are level-shifted, so that the level shifter array can be latched up. Also, since a number of gate lines are enabled, an overcurrent, called “rush current” having several hundred times the value as compared with a normal value, flows at the gate D-ICs
4
a
-
4
n
. Such a rush current has an adverse effect on circuit devices within the LCD and gives rise to an abnormal operation in the circuit devices. This causes a deterioration in the LCD.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a circuit for preventing rush current in liquid crystal display that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a rush current preventing circuit for a liquid crystal display that is suitable for eliminating a rush current when an initial power is applied to the liquid crystal display.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a rush current preventing circuit for a liquid crystal display includes output enable signal generating means for generating an output enable signal to control outputs of gate drive integrated circuits; start output enable signal generating means for generating a start output enable signal having at least a desired interval of disable pulse at the time of applying an initial power; and output enable signal switching means for switching the output enable signal and the start output enable signal corresponding to the start output enable signal.
According to another aspect of the present invention, a rush current preventing circuit for a liquid crystal display includes start output enable signal generating means for generating a start output enable signal having at least a desired interval of disable pulse at the time of applying an initial power; and output enable signal combining means for combining an output enable signal with the start output enable signal and for applying the combined output enable signal to the gate drive integrated circuits.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4495626 (1985-01-01), Brunin et al.
patent: 4731797 (1988-03-01), Jaffre et al.
patent: 5726677 (1998-03-01), Imamura
patent: 5748902 (1998-05-01), Dalton et al.
patent: 5917364 (1999-06-01), Nakamura
patent: 6040828 (2000-03-01), Park
patent: 6124840 (2000-09-01), Kwon
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patent: 0 872 793 (1998-10-01), None
patent: 07-199148 (1995-08-01), None
patent: 08-304773 (1996-11-01), None
patent: 09-233146 (1997-09-01), None
patent: 10-190751 (1998-07-01), None
patent: WO 92/09162 (1992-05-01), None
patent: WO 97/13347 (1997-04-01), None
patent: WO 97/13348 (1997-04-01), None
United Kingdom Patent Office Search Report dated Oct. 12, 1999.
Korean Patent Office Search Report dated Sep. 28, 2000.
LG. Philips LCD Co. Ltd.
Long Aldridge & Norman LLP
Zamani Ali
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