Circuit for preventing operation of parasitic components in inte

Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Signal transmission integrity or spurious noise override

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Details

327535, 327546, 327566, 257372, 257394, 257547, H03K 1716

Patent

active

056614306

ABSTRACT:
An integrated circuit including a power stage, a low-voltage component separated from the power stage by an isolating region and a reference potential region at a reference potential. The power stage includes an N-type substrate region which may be biased to a terminal voltage with respect to the reference potential and the isolating region has P-type conductivity. The low-voltage component includes an N-type input region receiving an input voltage. The input voltage and the terminal voltage may oscillate a few tens of volts above or below the reference potential and turn on parasitic transistors. To prevent turning on of the parasitic transistors, switchable conductive paths are interposed between the isolating region on the one hand, and the substrate region, the input region and the reference potential region on the other, for electrically connecting the isolating region to one of the substrate region, input region and reference potential region which presents instant by instant the lowest potential.

REFERENCES:
patent: 3990092 (1976-11-01), Yoshimura
patent: 5051612 (1991-09-01), Agiman
patent: 5132866 (1992-07-01), Raciti et al.
patent: 5475273 (1995-12-01), Paparo et al.

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