Circuit for preventing latch-up of parasitic thyristor formed in

Details Circuit for preventing latch-up of parasitic thyristor formed in Circuit for preventing latch-up of parasitic thyristor formed in

1988-03-09

1990-05-01

DeBoer, Todd E.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Impedance insertion

361 19, 361104, 361111, 361141, 323360, 338325, 505850, 505881, 505869, H02H 902

Patent

active

049223674

ABSTRACT:
A CMOS circuit including a variable conductor means interposed between a power supply and the CMOS circuit. The CMOS circuit comprises a P channel MOS FET and an N channel MOS FET laterally formed on the surface of a semiconductor substrate, inherently producing a parasitic thyristor which can be latched-up with destructive consequences under certain circumstances. The variable conductor means, interposed between the power supply and CMOS circuit, preferably includes a superconductor arranged to sharply switch to a normal conductor mode when the current level exceeds a critical current level, established to be less than the latch-up holding current of the parasitic thyristor, thereby to prevent latch-up.

REFERENCES:
patent: 3251715 (1966-05-01), Miles et al.
patent: 3703664 (1972-11-01), Cronin
patent: 3925707 (1975-12-01), Bhake et al.

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