Circuit for preventing latch-up in DC-DC converter

Details Circuit for preventing latch-up in DC-DC converter Circuit for preventing latch-up in DC-DC converter

2008-06-10

2008-06-10

Vu, Bao Q (Department: 2838)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S530000, C327S545000, C327S564000

Reexamination Certificate

active

07385434

ABSTRACT:
There is provided a circuit for preventing latch-up in a DC-DC. The circuit for preventing a latch-up phenomenon in a DC-DC converter, the DC-DC converter having a first and a second DC-DC converters coupled with each other in one chip for receiving an input voltage to generate a positive voltage and a negative voltage, respectively, in which a parasitic block with a PNP transistor and an NPN transistor causing a latch-up phenomenon is embedded, the circuit includes a first pathway for controlling an input current flowing to the first DC-DC converter from an input terminal receiving the input voltage in order that the PNP transistor is turned on and the NPN transistor is not turned on; and a second pathway for supplying the input current to the first DC-DC converter intactly at a timing that both the positive and negative voltages reach target voltages.

REFERENCES:
patent: 5304859 (1994-04-01), Arimoto
patent: 5689209 (1997-11-01), Williams et al.
patent: 5767733 (1998-06-01), Grugett
patent: 6191615 (2001-02-01), Koga
patent: 6373479 (2002-04-01), Moon
patent: 6377112 (2002-04-01), Rozsypal
patent: 10-2004-0115903 (2004-12-01), None

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