Electrical computers: arithmetic processing and calculating – Electrical analog calculating computer – Particular function performed
Reexamination Certificate
2001-07-13
2004-10-12
Ngo, Chuong Dinh (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical analog calculating computer
Particular function performed
Reexamination Certificate
active
06804697
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to electronic systems and in particular it relates to precise measurements of the average value of the outputs of multiple circuit unit elements.
BACKGROUND OF THE INVENTION
Dynamic Element Matching (DEM) is a technique frequently employed in applications where a number of unit elements exhibiting a certain degree of mismatch in their absolute values are to be matched to a certain resolution finer than the mismatch tolerance. Such situations occur, for example, in the capacitor arrays of multiplying digital-analog converter units (MDACs) of switched-capacitor analog-digital converts (ADCs), in the unit elements of multibit quantizer digital-analog converters (DACs) of sigma-delta feedback loops, etc. These situations are ideal for DEM implementations because they involve a large number of nominally identical unit elements. By randomly switching between these unit elements, all elements are effectively matched to the mean value of all the elements, reducing tones and harmonic distortion in the output spectrum. The tradeoff is an increase in noise level, since the energy present in the tones is not removed, and is randomized and spread over the entire noise floor. This tradeoff is often acceptable since the tones are the more serious factor limiting spectral performance.
DEM is not, however, straightforward to apply to all potential application areas where it might be of use. In particular, one example of such an area is that of segmented high speed and resolution DACs. In these applications, it is easy enough to apply DEM to the thermometer coded most significant bits (MSBs), but it is usually problematic to get the mean value of the MSBs to match the sum total of the least significant bits (LSBs), depending on the implementation. The matching between the MSBs and the sum of the LSBs is required for good static and dynamic linearity; matching inferior to the resolution required would show up statically as integral and differential non-linearity errors (INL and DNL respectively) and dynamically as tones in the spectral response once again. Unfortunately, in most circuit architectures and implementations, the LSBs cannot be integrated in the DEM scheme, owing to the existence of different time constants in the LSB circuit which would exist at the DEM multiplexing node where the LSB current divider circuit is being switched, and the effective sum total LSB value would be matched to the mean of the MSBs only for very low clock frequencies where this time constant would be negligible.
Shou et al. (U.S. Pat. No. 5,521,543) describe an averaging circuit composed of a number of parallel CMOS inverters with a common shorted output node. Such a circuit is capable of measurement of the average value, but the measurement is not precise owing to the inverter gain. Moreover, there is no provision for precise replication of the average value. Finally, the technique depends on the use of CMOS inverters and is not readily adapted to use in a current signal environment. Caruso (U.S. Pat. No. 5,298,814) describes a similar circuit with similar limitations.
Niiho et al. (U.S. Pat. No. 4,523,108) describes a circuit which uses a weighted summer as a form of averaging circuit. This allows for measurement of an average input value; there is, however, only provision of comparison to another signal, not replication of the averaged signal. This circuit is also not suitable for time-averaging applications such as DEM environments.
SUMMARY OF THE INVENTION
Generally, and in one form of the invention, the averaging circuit includes: input signal nodes for providing input signals; a multiplexing circuit coupled to the input signal nodes for switching between the input signals to create a time waveform; a low pass filter coupled to an output of the multiplexing circuit for filtering the time waveform to create an average signal; and an average replication circuit coupled to an output of the low pass filter.
REFERENCES:
patent: 3366951 (1968-01-01), Lhermitte et al.
patent: 3371200 (1968-02-01), Funk
patent: 3686493 (1972-08-01), Schmid
patent: 4001605 (1977-01-01), Thomas et al.
Bugeja Alexander
Chaudhry Irfan A.
Fares Mounir
Tsay Ching-yuh
Brady III W. James
Ngo Chuong Dinh
Stewart Alan K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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