Circuit for plug/play in peripheral component interconnect bus

Details Circuit for plug/play in peripheral component interconnect bus Circuit for plug/play in peripheral component interconnect bus

1996-06-26

1998-03-31

Harvey, Jack B.

395283, G06F 1300

Patent

active

057348413

ABSTRACT:
A circuit or plug/play (P/P) in a PCI bus which can store information in a PCI master/target device so that an address input board or component installed in a PCI local bus necessary for developing an information processing system adopting the PCI bus can support complete automatic, the circuit including controlling means for generating a plurality of latch enabling signals having a predetermined delay time, in accordance with a PCI reset signal, a clock signal and an address signal for reading data, input generating means having a plurality of input generating blocks and generating a plurality of data to be written in corresponding latches, in accordance with the PCI reset signal, data latching means having a plurality of latches, constituted by a plurality of latch groups corresponding to the plurality of input generating blocks, for writing data applied from the input generating means, in accordance with the latch enabling signals from the controlling means; and a PCI interface for reading and outputting corresponding data written in the respective latch groups in the latching means, in accordance with the address signal for reading externally supplied data.

REFERENCES:
patent: 4607348 (1986-08-01), Sheth
patent: 4730317 (1988-03-01), Desyllas et al.
patent: 5379384 (1995-01-01), Solomon

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