Circuit for phase locking a clock signal to a series of pulses

Details Circuit for phase locking a clock signal to a series of pulses Circuit for phase locking a clock signal to a series of pulses

1986-10-27

1987-12-08

LaRoche, Eugene R.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

331 25, H03L 708

Patent

active

047120762

ABSTRACT:
A circuit for phase locking a clock signal to a series of data pulses includes a wide band signal generator, a power supply, a flip-flop, a loop filter and a voltage controlled oscillator ("VCO"). The circuit adds current or subtracts current from the loop filter which controls the voltage across the VCO. The voltage across the VCO determines the frequency of the clock signal which it outputs. During the PLO sync zone, the circuit adds or subtracts increased amounts of current from the loop filter during every other pulse to cause greater amounts of correction in the frequency of the clock signal during every other pulse. The wide band signal generator, which includes a component which decays over time, operates only during the PLO sync zone. The circuit uses a flip-flop triggered by each data pulse to either send the current from the wide band signal generator to ground or add it to the constant current level produced by the power supply.

REFERENCES:
patent: 4593254 (1986-06-01), Coburn

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