Static information storage and retrieval – Floating gate – Particular biasing
Patent
1994-03-17
1995-07-11
Popek, Joseph A.
Static information storage and retrieval
Floating gate
Particular biasing
365182, 36518905, 36518912, 365239, 365240, G11C 1134
Patent
active
054327415
ABSTRACT:
A circuit for programming an EEPROM 42 which is used to provide trim adjustment for an integrated circuit (IC). The programming circuit provides the capability of programming the EEPROM 42 indefinitely, employing interfaces which are available even after the IC is packaged and encapsulated. Furthermore, it provides the manufacturer or enduser the capability of disabling the programming function permanently, to thereby prevent any inadvertent modifications of the EEPROM 42 data. The programming circuit includes a one-bit EEPROM 32, a nonvolatile memory element which retains its programmed logic state whether or not it is powered up. EEPROM 32 is set during final probe test by the application of a voltage to a probe pad 30 coupled to its set input terminal. Probe pad 30 is exposed such that it may be contacted by a probe prior to IC encapsulation, but is inaccessible after encapsulation. So long as EEPROM 32 is set, EEPROM 42 may be modified upon receipt of a unique address from the system data bus followed by programming data for EEPROM 42. When EEPROM 32 is reset, the programming function of EEPROM 42 is permanently disabled. In a first embodiment, EEPROM 32 is reset by setting a predetermined one of the EEPROM 42 bits to a specified logic state. In a second embodiment, EEPROM 32 is reset by the receipt of another unique address decode from the system data bus.
REFERENCES:
patent: 5283759 (1994-02-01), Smith
Devore Joseph
Marshall Andrew
Brady III W. James
Donaldson Richard L.
Maginniss Christopher L.
Niranjan F.
Popek Joseph A.
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