Circuit for optimizing a delay line used to de-skew received...

Details Circuit for optimizing a delay line used to de-skew received... Circuit for optimizing a delay line used to de-skew received...

2006-03-14

2006-03-14

Vo, Don N. (Department: 2631)

Pulse or digital communications

Testing

C375S354000

Reexamination Certificate

active

07012956

ABSTRACT:
Delay circuits have programmable delay elements to delay data signals so a clock samples the data signals in the middle of the eye window pattern. The clock is frequency divided by two, generating a divided clock coupled to a clock delay circuit and a data delay circuit generating a toggle clock and a delayed toggle clock that are sampled with the clock signal. A state machine varies the number N of delay elements selected in the data delay circuit until successive samples of the toggle clock and the delay toggle clock have opposite logic stages. The resulting number N is the number of delay elements required to generate a delay equal to one period of the clock. The delay of each delay element is adjusted using adjustment control signals until an N is generated that is within a predetermined range. The adjustment control signals are distributed to the data delay circuits.

REFERENCES:
patent: 6600681 (2003-07-01), Korger et al.
patent: 6889334 (2005-05-01), Magro et al.
patent: 2004/0239388 (2004-12-01), Lee
patent: 2005/0099210 (2005-05-01), Fetzer et al.

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