Boots – shoes – and leggings
Patent
1985-09-16
1989-01-24
Harkcom, Gary V.
Boots, shoes, and leggings
364754, 364761, G06F 738
Patent
active
048005150
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The present invention relates to a circuit for operating finite fields which is used for an encoder and a decoder of error correction codes.
When a digital video signal, a digital audio signal or the like is recorded or reproduced, adjacent codes, Reed Solomon codes or the like have been put to practical use as error correction codes. In the encoder of these error correction codes, parity data (redundant data) is generated. In the decoder, a syndrome is generated from the received word including parity data and the error correction is performed using this syndrome. Circuit for operating finite fields is used as a hardware of these parity generating circuit, syndrome generating circuit and error correcting circuit. The finite field is the field having p.sup.m elements derived from the primitive polynomial P(x) of a degree of m. The case of (p=2) is important with respect to the error correction codes and this invention, accordingly, is applied to the finite field of (p=2).
A continued product of which an involution of .alpha. was multiplied to an arbitrary element .alpha..sup.i over the finite field is used as the circuit for operating finite fields which is used for the encoder and decoder. For this multiplication, .alpha..sup.i is inputted to a ROM and thereby obtaining an exponent i. Thus, a ROM is needed and there is a drawback such that the circuit scale becomes large. On one hand, in case of a degree of m, a discrimination in mod. (2.sup.m -1) is required with regard to the exponent and there is a drawback such that this discrimination becomes troublesome because it is not the involution of 2.
The Reed Solomon codes are used as the error correction codes in the main channel of a digital audio disc (referred to as a compact disc), and the decoding circuit has an arrangement of a hard wired method using a TTL circuit. Since recently, the operation speed of a microprocessor has been remarkably improved and also the memory capacity has been extremely increased, if the error correcting circuit is constituted by a general microprocessor, there is no need to design a new LSI and the cost can be reduced. In particular, the data rate of the subcoding signal of the foregoing digital audio disc is lower than that in the main channel. In addition, in case of recording digital data such as video data or the like using the digital audio disc, a temporary buffering of the reproduced data can be performed. In these cases, the decoder of the error correction codes can be realized by a general microprocessor.
It is therefore an object of the present invention to provide a circuit for operating finite fields in which the necessary quantity of memory such as a ROM, a register or the like is reduced and the circuit scale is made small.
Another object of the invention is to provide a circuit for operating finite fields in which by reducing the necessary number of memories, the number of steps is decreased and thereby enabling the processing speed in arithmetic operation to be made high.
Still another object of the invention is to provide a circuit for operating finite fields in which a multiplication or a division in relation to arbitrary two elements over the finite field can be performed by way of a program stored method.
Further another object of the invention is to provide a circuit for operating finite fields which is suitable for an encoder and a decoder of error correction codes.
SUMMARY OF THE INVENTION
The present invention relates to a circuit for operating finite fields which performs a multiplication or a division in relation to arbitrary elements .alpha..sup.i and .alpha. over a finite field (where, .alpha. is a root of a primitive polynomial of the finite field),
wherein this circuit includes: an accumulator to store the arbitrary element .alpha..sup.i ; an adder to perform a module 2 addition of the contents of the accumulator and represented by a vector the primitive polynomial; and a control section to control the bit-shift of the accumulator and the operation of the adder i
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3rd International Conference, "The Technology and Applications of Charge Coupled Devices", Sep. 1976, pp. D1-D13.
Furuya Tsuneo
Hori Katsuya
Harkcom Gary V.
Mai Tan V.
Sony Corporation
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