Circuit for multiplexing a tapped differential delay line to...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform

Reexamination Certificate

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C327S277000

Reexamination Certificate

active

07088163

ABSTRACT:
A method and circuit to adjust timing between received differential data and clock signals to compensate for differences between transmission paths of data and clock signals. According to one embodiment, a timing adjustment circuit includes a decoder, a differential delay stage and a converter stage. The decoder is arranged to select one of the differential tri-state buffers, which provides the signal with a selected delay to a differential-to-single-ended converter. The converter provides properly a timing-adjusted signal to other circuits for further processing. Two current sources may be employed instead of resistive loads for the converter stage resulting in increased operating frequency and decreased power dissipation.

REFERENCES:
patent: 5179303 (1993-01-01), Searles et al.
patent: 5854797 (1998-12-01), Schwartz et al.
patent: 6073259 (2000-06-01), Sartschev et al.
patent: 6351191 (2002-02-01), Nair et al.
patent: 6677791 (2004-01-01), Okuda et al.
patent: 6756818 (2004-06-01), Liu et al.
patent: 6784714 (2004-08-01), Nakamura
patent: 6900679 (2005-05-01), Watarai

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