Circuit for modifying a clock signal to achieve a...

Details Circuit for modifying a clock signal to achieve a... Circuit for modifying a clock signal to achieve a...

2005-05-17

2005-05-17

Nuton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

C327S263000

Reexamination Certificate

active

06894548

ABSTRACT:
The present invention accepts timing and clock signals with a desired frequency and undesired duty cycle CLKIN, and outputs a clock signal CLKOUT with the desired frequency and desired duty cycle. If the clock signal is known to have a duty cycle of greater than 50%, one exemplary embodiment of the present invention delays the rising edge of the clock signal so as to produce a clock signal with a 50% duty cycle. One exemplary embodiment of the present invention comprises a charge pump integrator (102) configured in a feedback loop, the output of the charge pump integrator (102) operable as a controlling node to delay inverter (115). If the clock signal CLKIN at the input of the circuit has a duty cycle of greater than 50%, then the charge pump integrator (102) will, through PBIAS, cause delay inverter115to delay of the rising edge of CLKIN through delay inverter (115). The charge pump integrator, through PBIAS, drives the duty cycle of the clock signal towards 50%.

REFERENCES:
patent: 6242960 (2001-06-01), Bae
patent: 6414522 (2002-07-01), Nguyen et al.
patent: 6529058 (2003-03-01), Gupta
patent: 6617935 (2003-09-01), Nguyen
patent: 6664834 (2003-12-01), Nair et al.
patent: 6670838 (2003-12-01), Cao

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