Circuit for minimizing filter capacitance leakage induced...

Details Circuit for minimizing filter capacitance leakage induced... Circuit for minimizing filter capacitance leakage induced...

2006-11-07

2006-11-07

Pascal, Robert (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C331S105000, C327S157000

Reexamination Certificate

active

07132896

ABSTRACT:
A method, an apparatus, and a computer program are provided to minimize filter capacitor leakage in a Phased Locked Loop (PLL). In high frequency processors and devices, filter leakage currents can cause substantial problems by causing PLLs to drift out of phase lock. To combat the leakage currents, a dummy filter and other components are employed to provide additional charge or voltage to a low pass filter during lock. The provision of the charge or voltage exponentially decreases the rate of decay of voltage across the low pass filter caused by leakage currents.

REFERENCES:
patent: 5461344 (1995-10-01), Andoh
patent: 6538518 (2003-03-01), Chengson
patent: 6963232 (2005-11-01), Frans et al.

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