Oscillators – Ring oscillators
Reexamination Certificate
1999-07-22
2001-05-15
Grimm, Siegfried H. (Department: 2817)
Oscillators
Ring oscillators
C324S617000, C324S633000, C327S265000, C365S201000, C368S118000, C368S120000, 37
Reexamination Certificate
active
06232845
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to methods and circuit configurations for measuring signal propagation delays, and in particular for measuring signal propagation delays through synchronous memory elements.
BACKGROUND
Integrated circuits (ICs) are the cornerstones of myriad computational systems, such as personal computers and communications networks. Purchasers of such systems have come to expect significant improvements in speed performance over time. The demand for speed encourages system designers to select ICs that boast superior speed performance. This leads IC manufactures to carefully test the speed performance of their designs.
FIG. 1
depicts a conventional test configuration
100
for determining the signal propagation delay of a test circuit
110
in a conventional IC
115
. A tester
120
includes an output lead
125
connected to an input pin
130
of IC
115
. Tester
120
also includes an input line
135
connected to an output pin
140
of IC
115
.
Tester
120
applies an input signal to input pin
130
and measures how long the signal takes to propagate through test circuit
110
from input pin
130
to output pin
140
. The resulting time period is the timing parameter for test circuit
110
, the path of interest. Such parameters are typically published in literature associated with particular ICs and/or used to model the speed performance of circuit designs that employ the path of interest.
Conventional test procedures are problematic for at least two reasons. First, many signal paths within a given IC are not directly accessible via input and output pins, and therefore cannot be measured directly. Second, testers have tolerances that can have a significant impact on some measurements, particularly when the path of interest is short. For example, if a tester accurate to one nanosecond measures a propagation delay of one nanosecond, the actual propagation delay might be any time between zero and two nanoseconds. In such a case the IC manufacturer would have to assume the timing parameter was two nanoseconds, the worst-case scenario. If ICs are not assigned worst-case values, some designs will fail. Thus, IC manufacturers tend to add relatively large margins of error, or “guard bands,” to ensure that their circuits will perform as advertised. Unfortunately, this means that those manufacturers will not be able to guarantee their full speed performance, which could cost them customers in an industry where speed performance is paramount.
Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that may be programmed by a user (e.g., a circuit designer) to perform specified logic functions. One type of PLD, the field-programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) that are programmably interconnected to each other and to programmable input/output blocks (IOBs). This collection of configurable logic is configured by loading configuration data into internal configuration memory cells that define how the CLBs, interconnections, and IOBs are configured.
Each programming point, CLB, interconnection line, and IOB introduces some delay into a signal path. The many potential combinations of delay-inducing elements make timing predictions particularly difficult. FPGA designers use “speed files” that include resistance and capacitance values for the various delay-inducing elements and combine them to establish delays for desired signal paths. These delays are then used to predict circuit timing for selected circuit designs implemented as FPGA configurations. FPGA timing parameters are assigned worst-case values to ensure FPGA designs work as indicated.
Manufacturers of ICs, including FPGAs, would like to guarantee the highest speed performance possible without causing ICs to fail to meet the guaranteed timing specifications. More accurate measurements of circuit timing allow IC designers to use smaller guard bands to ensure correct device performance, and therefore to guarantee higher speed performance. There is therefore a need for a more accurate means of characterizing IC speed performance.
SUMMARY
The present invention provides an accurate means of measuring IC speed performance. The inventive circuit is particularly useful for testing programmable logic devices, which can be programmed to include a device for testing a majority of the requisite test circuitry.
In accordance with an embodiment of the invention, a number of synchronous components are configured in a loop to form a free-running ring oscillator. Each synchronous component clocks a subsequent synchronous component in the ring; the subsequent synchronous component responds by clocking the next component in the ring and by clearing the previous component to prepare it for a subsequent clock. The oscillator thus produces an oscillating test signal in which the period includes the clock-to-out delays of the synchronous components as well as the delays of the circuit configuration. This combination provides an effective means for measuring the clock-to-out delays of synchronous components.
Synchronous components can exhibit different propagation delays depending upon whether they are configured to clock in response to rising or falling edges. Some embodiments of the present invention address this problem by separately measuring the clock-to-out delays associated with rising and falling edges. The worst-case delay associated with a given component can then be expressed as the longer of the two. Knowing the precise worst-case delay allows IC designers to minimize the guard band and consequently guarantee higher speed performance.
Clock-to-out delays are not the only propagation delays of interest. Various other type of synchronous and asynchronous signal paths should also be characterized to produce speed files that may be employed to accurately predict IC speed performance. For example, the speeds at which a memory element can be preset, cleared, written to, read from, or clock enabled can also impact speed performance. Other embodiments of the invention are therefore adapted to produce delay data indicative of these additional memory-cell characteristics.
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Bauer Trevor J.
Kingsley Christopher H.
Patrie Robert D.
Wells Robert W.
Behiel Arthur J.
Grimm Siegfried H.
Xilinx , Inc.
Young Edel M.
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