Circuit for masking a dirty status indication provided by a cach

Details Circuit for masking a dirty status indication provided by a cach Circuit for masking a dirty status indication provided by a cach

1996-05-14

1997-11-25

Swann, Tod R.

Boots, shoes, and leggings

364DIG1, 364DIG2, 3642434, 395468, 395420, 39518201, G06F 1120, G06F 1200

Patent

active

056921543

ABSTRACT:
Circuitry which corrects a problem in the 82424TX Cache and Dram Controller (CDC) from Intel with the addition of only minor circuitry which can be used externally or internally and which allows proper operation under all conditions. Combinatorial logic is provided to block the dirty bit provided by the dirty Static Random Access Memory (SRAM) when the processor is performing a noncacheable access as indicated by the Page Cache Disable (PCD) bit. In certain cases the PCD bit is ignored and the stored dirty bit is passed without blocking: when the AHOLD signal is asserted, indicating that an address snoop operation is occurring, and when the BOFF* signal is asserted, indicating that a cache flush or writeback operation is occurring. Thus, the dirty bit provided by the dirty SRAM when the processor is performing a non-cacheable access is selectively blocked in certain instances to ensure cache coherency.

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patent: 5423019 (1995-06-01), Lin
Intel Corp., 82420 PCI Set Cache/Memory Subsystem, Entire Book, 1993.

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