Circuit for localizing errors in Reed-Solomon decoders

Details Circuit for localizing errors in Reed-Solomon decoders Circuit for localizing errors in Reed-Solomon decoders

1995-06-22

1998-04-07

Baker, Stephen M.

Excavating

H03M 1300

Patent

active

057373434

ABSTRACT:
In a Reed-Solomon error correction system, the coefficients of the syndrome polynomial of degree 2t-1 are stored in a first set of registers R, coefficients 0,0 . . . ,0,1,0 are stored in a second set of registers .lambda., and a first number is stored in a counter. Coefficients 1,0 . . . ,0 are stored in a third set of registers Q, zeroes are stored in a fourth set of registers .mu., and a number exceeding the first number by 1 is stored in an indicator register.

REFERENCES:
patent: 4504948 (1985-03-01), Patel
patent: 4649541 (1987-03-01), Lahmeyer
patent: 4747103 (1988-05-01), Iwamura et al.
patent: 4868828 (1989-09-01), Shao et al.
patent: 4888778 (1989-12-01), Brechard et al.
patent: 5170399 (1992-12-01), Cameron et al.
patent: 5185711 (1993-02-01), Hattori
patent: 5325373 (1994-06-01), Iwamura et al.
patent: 5442578 (1995-08-01), Hattori
patent: 5504758 (1996-04-01), Inoue et al.
patent: 5517509 (1996-05-01), Yoneda
Jeong et al., "VLSI Array Synthesis for Polynomial GCD Computation and Application to Finite Field Division", IEEE Transactions on Circuits and Systems:--I Fundamental theory and Applications, vol. 41, No. 12, Dec. 1994, pp. 891-897.
Shao et al., "A VLSI Design of a Pipeline Reed-Solomon Decoder", IEEE Transactions on Computers, vol. c-34, No. 5, May 1985, pp. 393-403.
Whiting, "Bit-Serial Reed Solomon Decoders in VLSI", Ph.D. Thesis, California Institute of Technology, 1985, pp. 56-57, Dec. 1985.
French Search Report from French Patent Application No. 94 08122, filed Jun. 27, 1994.
GEC Journal of Research (Incorporating Marconi Review), vol. 9, No. 3, 1992, Great Baddow Chemsford GB, pp. 172-184, Arambepola & Choomchuay, "Algorithms and Architectures for Reed-Solomon Codes".
Proceedings Of the Int. Conf. On Application Specific Array Processors, Sep. 5, 1990, Princeton, NJ, US Nelson, Rahman & McQuade "Systolic Architectures For Decoding Reed-Solomon Codes".
IEEE Transactions On Computers, vol. 37, No. 10, Oct. 1988, New York, US, pp. 1273-1280, Shao & Reed "On The VLSI Design Of A Pipeline Reed-Solomon Decoder Using Systolic Arrays".

Affiliated with

Also associated with

Rating

Circuit for localizing errors in Reed-Solomon decoders does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit for localizing errors in Reed-Solomon decoders, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit for localizing errors in Reed-Solomon decoders will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-20449