Circuit for limiting the deviation of logic voltages

Details Circuit for limiting the deviation of logic voltages Circuit for limiting the deviation of logic voltages

1985-12-02

1986-12-02

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307552, 307560, 307564, 307363, H03K 508

Patent

active

046267140

ABSTRACT:
A circuit is provided for limiting logic voltage deviations in so called very low consumption and ultra high speed DCFL logic circuits. The limiter circuit comprises, mounted in series between a voltage source and ground, a resistor and a normally off field effect transistor. The source of the transistor is grounded. The gate is connected to the drain which forms the output of the limiter circuit. The output voltage, which forms the high logic level, is less than or equal to three times the threshold voltage of the transistor if the current which flows through the load is less than or equal to twice the product of the transconductance of the transistor multiplied by its threshold voltage.

REFERENCES:
patent: 3518449 (1970-06-01), Chung
patent: 3987310 (1976-10-01), Peltier et al.
Patents Abstracts of Japan, vol. 7, No. 247, (E208) (1392) Nov. 2, 1983; & JP-A-58 136 139 (Nippon Denki K.K.) 13-08-83.
Patent Abstracts of Japan, vol. 1, No. 58, Jun. 6, 1977, p. 67 E 77; & JP-A-52 2270 (Hitachi Seisakusho K.K.) 08-01-1977.
Patents Abstracts of Japan, vol. 5, No. 86, (E-60) (758) Jun. 5, 1981; & JP-A-56 34 235 (Nippon Denki K.K.) 06-04-1981.
E.D.N. Electrical Design News, vol. 39, No. Jun. 3, 1984, pp. 225-232, Boston Mass., US; J Haight: "GaAs Logic Characteristics Result in Integration Problems."

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