Circuit for limiting inrush current through a transistor

Details Circuit for limiting inrush current through a transistor Circuit for limiting inrush current through a transistor

2000-06-12

2001-05-01

Sterrett, Jeffrey (Department: 2838)

Electricity: power supply or regulation systems

External or operator controlled

Using a three or more terminal semiconductive device as the...

C323S908000

Reexamination Certificate

active

06225797

ABSTRACT:

THE FIELD OF THE INVENTION
The present invention generally relates to a power supply system for electronic devices, and more particularly, to a circuit for limiting the inrush surge current flowing from a power supply system through a transistor, such as a power metal oxide semiconductor field effect transistor (MOSFET), to a capacitive load.
BACKGROUND OF THE INVENTION
A power supply system typically includes transistor, such as a power metal oxide semiconductor field effect transistor (MOSFET), to couple a load to a power source. When the MOSFET is controlled to couple the load having a large capacitive component to the power source, the power MOSFET is fully enhanced and a high transient current, or an inrush surge current, typically flows from the power source to charge the capacitive component of the load. In the absence of any current limiter, the magnitude of the inrush surge current is dependent upon the source impedance, which is typically low. As a result of the inrush surge current, the power source voltage suddenly decreases, then increases relatively slowly as the capacitive load component charges. When a single power source supplies power to several parallel loads, the large inrush surge current which occurs when one load is connected to the single power source can cause the power source voltage to drop below the level needed for proper operation of other connected circuits. In addition, large current surges impose undesirable stress on components.
Complementary metal oxide semiconductor (CMOS) logic arrays present a large capacitive load to a power source that supplies power to the logic array. The large capacitive load is mainly due to the internal gate capacitance and associated de-coupling capacitors. In fact, the effective capacitance of large CMOS dynamic random access memory (DRAM) arrays can exceed the capacitance within the power supply. Printed circuit card de-coupling capacitors are another example of a large capacitive load.
Accordingly, it is known to limit inrush surge current in various ways. In one simple method of limiting inrush surge current, a resistor is connected in series with the capacitive load. When power is turned on to the capacitive load, the resistance limits the surge current. However, an undesirable voltage drop to the capacitive load results from this method. Additionally, unwanted power consumption (I
2
R losses) and heat generation are increased.
In a slight modification to the method above, a resistor with a negative temperature coefficient of resistance and significant thermal time constant is connected in series with the capacitive load. As current from the power source flows through the resistor, the resistor heats which decreases its resistance to thereby decrease the I
2
R power losses through the resistor. However, this arrangement is ineffective if the resistor is hot when the power is switched on. Additionally, the I
2
R power losses in the resistor, while being reduced in normal operation, may still be unacceptably high for certain power sensitive electronic devices.
Another method of limiting inrush surge current is to connect an inductor, which can be designed to provide very little power loss, in series with the load. However, in electronic devices, the necessary size and cost of such an inductor generally makes this alternative undesirable.
Another method of limiting inrush surge current is to connect a resistor in series with the load, and to connect a switch, such as relay contacts or a power transistor, in parallel with the resistor to bypass the resistor when the switch is closed during normal operation. The switch is typically closed after a fixed delay which is greater than the inrush surge current period or in response to the inrush surge current falling below a threshold level. If the switch is isolated after a fixed delay, this inrush surge current limiting method typically has an undesirably long fixed delay. On the other hand, an undesirably complicated and/or sensitive sensing and control circuit is required to control the switch in response to the inrush surge current falling below a threshold level.
Another method of limiting inrush surge current is to add a large amount of additional power supply de-coupling capacitance. However, this method of limiting inrush surge current adds significantly to the size, weight, and cost of the power supply, and can lead to power supply control loop instability.
A further method to limit current flow through a MOSFET is to connect a voltage divider in parallel with a series circuit including the power MOSFET and the capacitive load. A node of the voltage divider is connected to a control terminal of a control transistor. The control transistor has a load path connected between a gate and a source of the power MOSFET. The control transistor is controlled by the voltage at the node of the voltage divider such that if the drain-to-source voltage of the power MOSFET exceeds a pre-determined voltage value the control transistor conducts. Examples of such voltage divider configurations are described in the Leipold et al. U.S. Pat. No. 4,952,827 and the Tihanyi et al. U.S. Pat. No. 5,272,399, which are both herein incorporated by reference. Such circuit configurations are designed to prevent steady state overcurrent conditions rather than inrush surge current and additionally, include a significant number of components.
Adding additional MOSFET gate-to-source capacitance helps very little to limit the inrush surge current, since it mainly delays the onset rather than slowing the transition through the threshold region, permitting the MOSFET to transition from off to fully on over a short time period. Correspondingly, the load capacitance charges within the short MOSFET transition time period. Extending the period of time it takes for the MOSFET gate voltage to pass through the threshold region extends the time of the MOSFET's reduced current-passing capacity, allowing the capacitive load to charge more slowly at lower current levels. A resistor may be used to sense current, with a feedback path including an operational amplifier; however, such a solution requires a large number of components and adds additional voltage drop in the path between source and load that is not compensated for by the sense leads.
To avoid the shortcomings of the above-discussed techniques and for other reasons presented in the Description of the Preferred Embodiments, a need exits for a simple circuit, using a minimal number of components, and method to limit inrush surge current from a power supply system, through a power MOSFET, to a capacitive load.
SUMMARY OF THE INVENTION
The present invention provides a power supply system which provides power to a capacitive load. The power supply system includes a power source having a ground terminal coupled to a ground reference and a positive power terminal. A switch, such as a transistor, has a first terminal coupled to the power source power terminal, a second terminal coupled to the capacitive load, and a control terminal. A field effect transistor (FET) has a gate coupled to the second terminal of the transistor, a source coupled to the first terminal of the transistor, and a drain. A capacitor is coupled between the control terminal of the transistor and the drain of the FET.
In one embodiment, the transistor is a metal oxide semiconductor field effect transistor (MOSFET) having a drain as a the first terminal, a source as a second terminal, and a gate as the control terminal. The power supply system operates such that the FET diverts some of the MOSFET gate current while the MOSFET turns on, preventing the MOSFET from fully turning on, thus limiting the current through the MOSFET to charge the capacitive load. Charging the capacitor provides a delay time, after which, the MOSFET is allowed to turn on fully.
In one embodiment of the power supply system according to the present invention, the MOSFET is an N-channel power MOSFET; however, P-channel MOSFETs may also be used for certain applications. In one embodiment, the FET is a depletion mod

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