Circuit for interfacing with both TTL and CMOS voltage levels

Details Circuit for interfacing with both TTL and CMOS voltage levels Circuit for interfacing with both TTL and CMOS voltage levels

1982-08-20

1984-09-18

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307360, 307469, H03K 19094, H03K 1730, H03K 17693

Patent

active

044726473

ABSTRACT:
A voltage compatible circuit for providing TTL and CMOS level inputs and/or outputs is provided. An input signal level detection portion generates either a CMOS or a TTL mode signal in response to a voltage level selection signal. One or more input buffers and/or output buffers is coupled to the CMOS and TTL mode signals. The input buffers are responsive to input signals within predetermined CMOS voltage levels in response to a voltage level signal having at least a predetermined value determined by the input signal level detection portion and within predetermined TTL voltage levels otherwise. The output buffers provide output signals within predetermined CMOS voltage levels in response to a voltage level signal having at least a predetermined value determined by the input signal level detection portion and within predetermined TTL voltage levels otherwise. A reference voltage portion and a bias generator portion are coupled to the input and output buffers to provide the predetermined voltage levels.

REFERENCES:
patent: 4032795 (1977-06-01), Hale
patent: 4242604 (1980-12-01), Smith
patent: 4287439 (1981-09-01), Leuschner
patent: 4342926 (1982-08-01), Whatley
patent: 4380710 (1983-04-01), Cohen et al.
patent: 4392067 (1983-07-01), Price, Jr.

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