Circuit for initializing registers using two input signals for w

Details Circuit for initializing registers using two input signals for w Circuit for initializing registers using two input signals for w

1990-12-20

1994-04-12

Anderson, Lawrence E.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072721, 36424691, 3642486, 3642514, 3642608, 3642715, 364DIG1, 3649504, 364964, 395800, G06F 1300

Patent

active

053033507

ABSTRACT:
A circuit for initializing a D-latch of an input/output system. The circuit comprises first and second logic means, the first logic means generating an enable signal coupled to the clock input of the D-latch which changes state from inactive to active at a first time t1 and again at a subsequent time t2, in response to the system write control signal addressed to the D-latch and the system reset signal. The second logic means generates a local data signal, in response to the system reset signal and system data signal, to the data input of the D-latch. The D-latch is reset substantially at time t1 and the system data signal is strobed in the D-latch substantially at time t2.

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