Circuit for increasing the output current in MOS transistors

Details Circuit for increasing the output current in MOS transistors Circuit for increasing the output current in MOS transistors

1977-01-07

1977-12-13

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307205, 307251, 307DIG4, H03K 1712, H03K 1704, H03K 1728, H03K 1760

Patent

active

040631176

ABSTRACT:
In order to increase the output current of an MOS transistor, its gate is provided with a switched capacitor drive. A tri-state inverter is used to drive the output transistor gate from an input source. A pair of delay elements are cascaded to drive one input of a NOR gate, the other input of which is fed an undelayed signal. The NOR gate is used to switch a capacitor that is also coupled to the output transistor gate. The juncture between the delays is coupled to the control electrode of the tri-state inverter. During the first delay interval, the capacitor and the output transistor gate electrode are charged. Then after the second delay interval, which is shorter than the first, the capacitor is discharged into the output transistor gate electrode which is thereby driven substantially in excess of the conventional drive level.

REFERENCES:
patent: 3631267 (1971-12-01), Heimbigner
patent: 3646369 (1972-02-01), Fujimoto
patent: 3714466 (1973-01-01), Spence
patent: 3769528 (1973-10-01), Chu et al.
patent: 3778784 (1973-12-01), Karp et al.
patent: 3806880 (1974-04-01), Spence
patent: 3898479 (1975-08-01), Proebsting
Anderson, "FET Inverter and Driver Circuit", IBM Tech. Discl. Bull., vol. 16, No. 1, pp. 50-51; June 1973.

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