Circuit for increasing the apparent occupancy of a processor

Details Circuit for increasing the apparent occupancy of a processor Circuit for increasing the apparent occupancy of a processor

1975-10-30

1977-08-02

Chapnick, Melvin B.

Boots, shoes, and leggings

G06F 104

Patent

active

040400212

ABSTRACT:
An arrangement for measuring the load handling capacity of a stored program control process control system. The process control system is first operated in a monitor mode without any load in order to identify the instructions which must be executed independently of load and therefore, may be characterized as "overhead work" instructions. While operating in the no load or monitor mode, each instruction which is executed is flagged by placing "1" in a flag position of the instruction word. The machine includes provisions for executing instructions so flagged with standard machine timing and for executing unflagged instructions with extended machine timing. The unflagged instructions are termed "load related work" instructions and by extending the time required to execute such instructions, the apparent load to the machine is increased, increasing the machine's apparent occupancy. The time for executing a "load related work" instruction is extended by integral numbers of clock frames. Only the instruction execution clock signal timing is altered during the execution of "load related work" instructions and all other measurements of time which denote the absolute passage of time or "real-time" are maintained. Having characterized and identified the "overhead work" instructions, a load is presented and the machine operates as above described. Accordingly, the effect of a relatively small load on a processor may be magnified to varying degrees by establishing a variety of different delays in the execution of "load related work" instructions.

REFERENCES:
patent: 3372381 (1968-03-01), Raspanti
patent: 3582896 (1971-06-01), Silber
patent: 3623007 (1971-11-01), Eckhart et al.
patent: 3623017 (1971-11-01), Lowell et al.
patent: 3698007 (1972-10-01), Malcolm et al.
patent: 3701973 (1972-10-01), VON DER Pfordten
patent: 3715728 (1973-02-01), Fontaine et al.
patent: 3751645 (1973-08-01), Brandsma et al.
patent: 3845475 (1974-10-01), Massaloux
patent: 3932843 (1976-01-01), Trelut et al.
patent: 3932847 (1976-01-01), Smith
patent: 3946363 (1976-03-01), Hakozaki
"Organization of the No. 1 ESS Stored Program" in Bell System Technical Journal, Sept. 1964, pp. 1927-1928, 1943-1959 and 2005-2009.
Smith, R. M. "Data Processing System Timing Facility" in IBM Technical Disclosure Bulletin; vol. 14, No. 10, Mar. 1972; pp. 3071-3073.
Fangmeier, L. J. et al.; "Processor Control By Two Independent Phase-Locked Clocks" in IBM Tech. Discl. Bull.; vol. 14, No. 11, Apr. 1972; pp. 3394-3395.

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