Circuit for improving performance of an ECL-to-TTL translator

Details Circuit for improving performance of an ECL-to-TTL translator Circuit for improving performance of an ECL-to-TTL translator

1985-05-13

1987-07-07

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307567, 307317A, H03K 19092, H03K 19088

Patent

active

046789448

ABSTRACT:
A logic level translator having a fast rising edge at its output for converting ECL logic levels into TTL logic levels includes a switching transistor having its base adapted to receive an input logic level signal representative of an ECL signal, the collector of the switching transistor being connected to an output node. A clamp delay circuit is interconnected between the collector and the base of the switching transistor for inhibiting the switching transistor from receiving feedback current to its base so as to cause a faster turn-off, thereby producing a fast rising edge response at the output node during a high-to-low transition of the input logic level signal.

REFERENCES:
patent: 3534281 (1970-10-01), Hillhouse
patent: 4467223 (1984-08-01), Neely
patent: 4581550 (1986-04-01), Ferris et al.
Chang, "Diode/Transistor Buffer", IBM Disclosure Bulletin, vol. 19, No. 3, Aug. 1976, pp. 989-990.

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