Circuit for implementing a digital computer instruction

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340347DD, G06F 500, G06F 300

Patent

active

044082711

ABSTRACT:
Apparatus for implementing a single computer instruction for moving a binary number of from one to four characters, with the characters of a given binary number having either eight or nine bits per character, from storage in a word addressable memory to a designated addressable register. The characters of the binary number are stored in the word addressable memory with each word of memory being divided into four 9-bit bytes. The most significant character of the binary number can be stored in any designated byte position of a word location with the characters of the number stored in contiguous byte locations in descending order of significance. The apparatus causes the binary number to be stored in the designated addressable register with the binary number being right justified in that register. Higher order bit positions of the register not needed to store the bits of the binary number will have stored into them fill bits or the sign bit of the number.

REFERENCES:
patent: 3348207 (1967-10-01), Malcolm et al.
patent: 3573744 (1971-04-01), Rigazio
patent: 3638195 (1972-01-01), Brender et al.
patent: 4000487 (1976-12-01), Patterson et al.
patent: 4131940 (1978-12-01), Moyer
patent: 4250548 (1981-02-01), Kindell
patent: 4291370 (1981-09-01), Charles
patent: 4364025 (1982-12-01), Dalton

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