Electricity: motive power systems – Induction motor systems – Primary circuit control
Reexamination Certificate
2002-03-28
2003-12-23
Masih, Karen (Department: 2837)
Electricity: motive power systems
Induction motor systems
Primary circuit control
C318S723000, C318S722000, C318S254100
Reexamination Certificate
active
06667598
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a control circuit including a circuit which generates a three-phase PWM (pulse width modulation) signal, and more particularly to a control circuit including a circuit for generating a three-phase PWM signal, and a circuit for carrying out feedback control for a three-phase invertor motor when the three-phase PWM signal is generated.
2. Description of the Related Art
FIG. 1
is a block diagram of a conventional circuit for generating a three-phase PWM signal.
The circuit for generating a three-phase PWM signal is comprised of a timer
21
, a first compare register
22
, a second compare register
24
, a third compare register
26
, a fourth compare register
28
, a first buffer register
23
, a second buffer register
25
, a third buffer register
27
, a fourth buffer register
29
, an up- and down-counting flag
30
, a first circuit
31
for generating a PWM signal, a second circuit
32
for generating dead time, and a third circuit
33
for controlling an output to be transmitted from the circuit.
The timer
21
generates a carrier period having a PWM waveform. If a carrier wave has a triangular waveform, the timer
21
carries out counting-up and counting-down operations.
The first compare register
22
controls a period of the timer
21
. The first compare register
22
always makes comparison with an output transmitted from the timer
21
, and converts an operation to be carried out by the timer
21
from counting-up operation to counting-down operation, if the first compare register
22
detects coincidence with the output signal transmitted from the timer
21
.
The first compare register
22
generates first interruption
34
, and the timer
21
generates second interruption
35
.
The up- and down-counting flag
30
indicates a status of the timer
21
. While the timer
21
is in counting-up operation, the up- and down-counting flag
30
is in a low level, whereas while the timer
21
is in counting-down operation, the up- and down-counting flag
30
is in a high level.
The second compare register
24
generates a U-phase timing. The second compare register
24
always makes comparison with an output signal transmitted from the timer
21
, and outputs a coincidence signal or a one shot pulse signal, if the second compare register
24
detects coincidence with the output signal.
Similarly, the third compare register
26
generates a V-phase timing. The third compare register
26
always makes comparison with an output signal transmitted from the timer
21
, and outputs a coincidence signal or a one shot pulse signal, if the third compare register
26
detects coincidence with the output signal.
Similarly, the fourth compare register
28
generates a W-phase timing. The fourth compare register
28
always makes comparison with an output signal transmitted from the timer
21
, and outputs a coincidence signal or a one shot pulse signal, if the fourth compare register
28
detects coincidence with the output signal.
The coincidence signals generated by the second to fourth compare registers
24
,
26
and
28
are transmitted to the first circuit
31
. On receipt of the coincidence signals, the first circuit
31
generates a signal based on which positive-phase and opposite-phase signals in each of the phases are generated.
The signal generated in the first circuit
31
is transmitted to the second circuit
32
. Based on the received signal, the second circuit
32
generates a timing to which dead time is added. Herein, dead time means a time for preventing positive and opposite phases of an invertor from short-circuiting with each other.
The second circuit
32
transmits its output signal to the third circuit
33
, which then transmits U
0
, U
1
, V
0
, V
1
, W
0
and W
1
signals to terminals of a microcomputer.
FIG. 5
is a timing chart showing an operation of the timer
21
, coincidence timings in the compare registers
22
,
24
,
26
and
28
, and timings of the terminals.
A gap in a timing between U
0
and U
1
signals, a gap in a timing between V
0
and V
1
signals, and a gap in a timing between W
0
and W
1
signals are all equal to a dead time width.
As illustrated in
FIG. 5
, the first interruption
34
is generated by virtue of coincidence between the first compare register
22
and the timer
21
. A timing at which the first interruption
34
is generated is a summit of a triangular wave carrier.
The second interruption
35
is generated by virtue of under-flow in the timer
21
. A timing at which the under-flow is generated is a bottom of a triangular wave carrier.
In accordance with the timing chart of
FIG. 5
, the timer
21
makes triangular wave operation, and coincidence timings in the first to fourth compare registers
22
,
24
,
26
and
28
are symmetrical about a summit of the triangular wave. This is called a triangular wave carrier symmetrical mode.
A conventional circuit for generating a three-phase PWM signal operates in the above-mentioned manner.
A circuit for generating a three-phase PWM signal is generally designed to include a circuit for generating an analog-digital trigger, in order to conduct feedback control to a three-phase inverter motor.
Such a circuit for generating an analog-digital trigger has been conventionally used as an external circuit for a micro-computer. Because of recent demand of cost reduction, down-sizing of a substrate, and accurate control for effectively rotating a motor, it is presently required to conduct both control to a three-phase PWM signal and feedback control through a single micro-computer.
If feedback control is frequently conducted, a central processing unit (CPU) would have increased burden in dealing with data. Hence, there is also a demand of reduction in a time for dealing with data through software in CPU.
In particular, a system for simultaneously controlling a plurality of motors such as a fan motor or a compressor motor in an air-conditioner is accompanied with a serious problem of an increase in a time necessary for dealing with data through software in CPU.
In order to solve such a problem, for instance, Japanese Unexamined Patent Publication No. 9-121558 (A) has suggested a method of detecting a current in a PWM invertor by means of an analog-digital convertor.
In the suggested method, a current output from a PWM invertor is detected by an analog-digital convertor.
FIG. 3
is a block diagram illustrating a basic structure of a three-phase invertor motor. With reference to
FIG. 3
, a current output from a PWM invertor is detected at points Iu, Iv and Iw in the suggested method.
A timing at which a current output from a PWM invertor is detected is a lowest point in a PWM carrier. In other word, referring to
FIG. 5
again, a timing at which a current output from a PWM invertor is detected is only a point corresponding to the second interruption
35
.
However, it may be necessary to detect an output current of a PWM invertor at a point Ia in
FIG. 3
in dependence on whether the three-phase invertor motor include a sensor and further on a structure of a system.
However, there cannot be found, in the suggested method, a concept of deviating an analog-digital conversion timing to a particular timing associated with a PWM output. Hence, the suggested method is inevitably accompanied with a problem that the suggested method can be applied only to a system in which currents Iu, Iv and Iw are directly detected.
Japanese Unexamined Patent Publication No. 4-172995 (A) has suggested a method of adjusting a timing at which a current output from an inverter is detected. The suggested method is carried out by means of an inverter additionally including only one compare register which generates a timing at which analog-digital conversion is to be carried out.
However, the suggested method is accompanied with problems that a time necessary for dealing with data through software is unavoidably long, because the compare register has one-stage structure, it would be quite difficult to generate two or more analog-digital timings, bec
Masih Karen
NEC Electronics Corporation
Scully Scott Murphy & Presser
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