Circuit for generating test equalization pulse

Details Circuit for generating test equalization pulse Circuit for generating test equalization pulse

1983-12-01

1985-10-22

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307265, 324 73R, 365201, 365233, H03K 504, H03K 17693

Patent

active

045491011

ABSTRACT:
A circuit for generating an equalization pulse for test purposes uses an equalization pulse generator which generates an equalization pulse in response to receiving one or more address transition signals generated from an address transition. The address transition signals are received by a multi-input logic circuit which causes the equalization pulse to be present at least as long as a signal is present at one of the inputs. A test pad on the integrated circuit receives an externally generated test signal of variable duration. The test signal is coupled to an input of the logic circuit to generate the equalization pulse for the duration of the test signal.

REFERENCES:
patent: 4439727 (1984-03-01), Boyle
patent: 4450515 (1984-05-01), Takemae et al.
patent: 4465973 (1984-08-01), Countryman, Jr.
patent: 4489247 (1984-12-01), Ikeda et al.
patent: 4495642 (1985-01-01), Zellmer
patent: 4503339 (1985-03-01), Tsuge et al.
Thoma, "Strobe-Controlled Data Output Circuit", IBM Tech Disc Bull, vol. 22, No. 3, Aug. 1979, pp. 941-942.

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