Circuit for generating stretched clock phases on a cycle by cycl

Details Circuit for generating stretched clock phases on a cycle by cycl Circuit for generating stretched clock phases on a cycle by cycl

1990-03-19

1991-09-03

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307271, 377 47, 328 20, 328 63, H03K 302, H03K 364, H03K 513, H03L 7085

Patent

active

050457152

ABSTRACT:
A clock circuit for generating two clock signals, one (CLK) having stretched clock phases on a cycle by cycle basis, and the second (2X CLK) being a clock signal having a frequency twice the frequency of the first clock signal which is phase and edge coherent with the first clock signal, including the stretched clock phases. The circuit inputs a signal generated by an oscillator which is twice the frequency of the CLK signal which is then used to generate the CLK signal for use by a microprocessor, either phase of which can be stretched on demand, while the second 2X CLK signal remains phase coherent with the microprocessor CLK signal.

REFERENCES:
patent: 4604582 (1986-08-01), Strenkowski et al.
patent: 4691170 (1987-09-01), Riley

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