Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
2000-06-23
2002-04-30
Smith, Matthew (Department: 2825)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S269000
Reexamination Certificate
active
06380784
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory circuit, and more particularly, to a semiconductor memory circuit.
2. Background of the Related Art
In general, for rapid bit line sensing in a semiconductor memory device, an overdriving method is employed in which a sense amplifier is initially driven with a high voltage and then driven with a low voltage.
FIG. 1
is a schematic view of a related art control circuit for generating a sense amplifier control signal in a semiconductor memory. The related art semiconductor memory includes a delay
10
for delaying a sense amplifier enable signal SAEBi to output it after a predetermined time, and a logic unit
20
for logically combining the sense amplifier enable signal SAEBi and the delay signal to generate a first and a second sense amplifier control signals SAP
1
B and SAP
2
B.
The logic unit
20
includes a first NOR gate NR
1
for NORing the sense amplifier enable signal SAEBi and an output signal from the delay
10
, a first and a second inverters INV
1
and INV
2
for buffering the sense amplifier enable signal SAEBi and a fourth and a fifth inverters INV
4
and INV
5
for buffering an output signal from the first NOR gate NR
1
. A second NOR gate NR
2
NORs an output signal from the second and fifth inverters INV
2
and INV
5
. A third inverter INV
3
inverts an output signal from the second NOR gate NR
2
and outputs the first sense amplifier control signal SAP
1
B, and a sixth or eighth inverters INV
6
-INV
8
sequentially invert an output signal from the fifth inverter INV
5
to output a second sense amplifier control signal SAP
2
B.
The operation of the related art circuit for generating a sense amplifier control signal will now be described with reference to FIG.
2
.
FIG. 2
shows signal waveforms at points of
FIG. 1
in accordance with the related art.
First, when the sense amplifier enable signal SAEBi is activated with “low” level signal, the signal is outputted as a delay signal A
1
. The delay signal A
1
is delayed for a predetermined time tD through the delay
10
. The sense amplifier enable signal SAEBi and the delay signal A
1
are NORed by the first NOR gate NR
1
to output a signal B
1
.
The sense amplifier enable signal SAEBi is outputted as a buffered signal C
1
after passing through the first and second inverters INV
1
and INV
2
, and the signal B
1
is outputted as a buffered signal D
1
after passing through the fourth and fifth inverters INV
4
and INV
5
. The output signals C
1
and D
1
of the seconded and fifth inverters INV
2
and INV
5
are NORed by the second NOR gate NR
2
and inverted by the third inverter INV
3
, according to which a first sense amplifier control signal SAP
1
B is generated with a pulse width as long as the delay time tD of the delay
10
. The pulse width tD of the first sense amplifier control signal SAP
1
B becomes an overdriving interval tD of the sense amplifier. Meanwhile, the output signal D
1
of the fifth inverter INV
5
passes through the sixth to eighth inverters INV
6
-INV
8
to thereby generate the second sense amplifier control signal SAP
2
B.
Consequently, after the first sense amplifier control signal SAP
1
B is first activated to perform the overdriving for the predetermined time tD, the second sense amplifier control signal SAP
2
B is activated to control the sense amplifier when the first sense amplifier control signal SAP
1
B is disabled.
The first sense amplifier control signal SAP
1
B is outputted as a signal having a high level voltage through a level shifter and the second sense amplifier control signal SAP
1
B is outputted as a signal having a low level voltage. Therefore, to sense a bit line quickly, a bit line signal is amplified by using the first sense amplifier control signal SAP
1
B having the high level voltage, and then is amplified by using the second sense amplifier control signal SAP
2
B having a low level voltage.
As described above, the related art circuit for generating the sense amplifier control signal has various disadvantages. In the related art circuit for generating the sense amplifier control signal in the semiconductor memory, since the whole bank is simultaneously operated during the refresh operation, the current consumption is quite high at the overdriving interval that requires the high level voltage.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention is to provide a circuit for sense amplifier control signal for a semiconductor memory that reduces a refresh current.
Another object of the present invention is to provide a circuit for sense amplifier control signal for a semiconductor memory in which signal paths for normal and refresh operation are different.
Another object of the present invention is to provide a circuit for sense amplifier control signal for a semiconductor memory that reduces a pulse width of an overdriving interval in refresh operations.
Another object of the present invention is to provide a circuit for sense amplifier control signal for a semiconductor memory in which signal paths for a normal operation and a refresh operation are separately formed so that a pulse width of an overdriving interval in the refresh operation is reduced and a refresh current is reduced.
To achieve at least these and other advantages in a whole or in parts and in accordance with the purpose of the present invention, as embodied and broadly described herein, there is provided a sense amplifier control circuit, including a first delay that delays a sense amplifier enable signal for a first prescribed delay time, a second delay that delays an output signal from the first delay for a second prescribed delay time, and a logic circuit that determines a normal operation and a refresh operation of the circuit and logically processes a refresh control signal, the output signal of the first delay and an output signal of the second delay so that different overdriving intervals are set for the normal operation and the refresh operation, respectively.
To further achieve at least these and other advantages in a whole or in parts and in accordance with the purpose of the present invention, as embodied and broadly described herein, there is provided a circuit, including a first delay that delays an enable signal for a first prescribed delay time, a second delay that delays an output signal from the first delay for a second prescribed delay time, and a logic circuit that determines a first mode and a second mode of the circuit and logically processes a control signal, the output signal of the first delay and an output signal of the second delay so that different overdriving intervals are set for the first mode and the second mode, respectively.
To further achieve at least these and other advantages in a whole or in parts and in accordance with the purpose of the present invention, as embodied and broadly described herein, there is provided a method of operating a circuit for generating a sense amplifier control signal for a semiconductor memory, including delaying a sense amplifier enable signal for a first prescribed delay time, delaying the sense amplifier enable signal for a second prescribed delay time that is longer than the first prescribed delay time, determining a normal operation and a refresh operation of the circuit, and generating a reduced overdriving interval signal for the refresh operation relative to a normal overdriving interval signal set for the normal operation by logically processing a refresh control signal and the delayed sense amplifier enable signals.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those havi
Dinh Paul
Fleshner & Kim LLP
Hyundai Electronics Industries Co,. Ltd.
Smith Matthew
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