Circuit for generating read and signal and circuit for...

Details Circuit for generating read and signal and circuit for... Circuit for generating read and signal and circuit for...

2011-05-31

2011-05-31

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233130, C365S193000, C365S195000, C365S233500, C365S233110, C365S227000

Reexamination Certificate

active

07952957

ABSTRACT:
A circuit for generating a read end signal includes a clock transferring unit which receives a clock signal, a write/read status signal and an all bank precharge signal and outputs a delayed clock signal, a read signal detecting unit which receives a read pulse signal and the delayed clock signal and generates a read detection signal having a pulse width corresponding to a certain clock, and a read end signal generating unit which receives a first signal, the delayed clock signal and the read detection signal and generates a read end signal.

REFERENCES:
patent: 6958953 (2005-10-01), Retter et al.
patent: 2006/0104126 (2006-05-01), Park
patent: 2007/0210850 (2007-09-01), Lee
patent: 2009/0316503 (2009-12-01), Ku
patent: 11-016360 (1999-01-01), None
patent: 10-2001-0048881 (2001-06-01), None

Affiliated with

Also associated with

Rating

Circuit for generating read and signal and circuit for... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit for generating read and signal and circuit for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit for generating read and signal and circuit for... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2660476