Circuit for generating pulse having predetermined time period wi

Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Particular input circuit

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328 58, 328 61, 3281291, 307265, 377 20, H03K 2102, H03K 2110

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active

049791940

ABSTRACT:
A first input section inputs a first signal serving as a trigger. A second input section inputs second and third signals having phases opposite to each other to set a time period width. A first data hold section obtains a first hold output in response to the first and second signals respectively output from the first and second input sections. A second data hold section obtains a second hold output in response to the first and third signals respectively output from the first and second input sections. A determination section determines whether the first hold output from the first data hold section or the second hold output from the second data hold section is output first. A selection section selects the second or third signal from the second input section in accordance with a determination result from the determination section. A counter counts the second or third signal selected by the selection section to set a time period width of a pulse signal to be output, and generates the pulse signal to be output at a predetermined timing in response to the first and second hold outputs respectively output from the first and second data hold sections.

REFERENCES:
patent: 3868845 (1975-03-01), Shimizu
patent: 3968445 (1976-07-01), Sherman
patent: 4052676 (1977-10-01), Crittenden
patent: 4396909 (1983-08-01), Suzuki
patent: 4692710 (1987-09-01), Shvartsman
patent: 4870664 (1989-09-01), Hayashi
"High Speed Data Format Converter Circuit", IBM Technical Disclosure Bulletin, vol. 20, No. 11, Apr. 1987, pp. 5036.5039.
"Digitally Controlled Monostable", Applied Ideas, Electronic Engineering, No. 743, Nov. 1988, p. 26.
Patent Abstracts of Japan, vol. 6, No. 32, Feb. 26, 1982.

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