Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-11-13
2003-07-01
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S541000, C327S545000, C327S546000, C326S087000
Reexamination Certificate
active
06586986
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a circuit for generating internal power voltage in a semiconductor device, and more particularly to, a circuit for stably generating internal power voltage as low consumption power in a semiconductor device having a CMOS inverter.
2. Description of the Related Art
FIG. 1
is a diagram of a conventional circuit for generating internal power voltage. As shown in
FIG. 1
, the conventional circuit for generating internal power voltage comprises: a comparison unit
11
for comparing reference voltage, Vref, and internal voltage, Vint; a first current supply unit
12
for supplying external voltage Vext to internal voltage Vint according to an output signal from the comparison unit
11
; a buffer unit
13
for buffering the output signal from the comparison unit
11
and for outputting the result; a second current supply unit
14
for supplying external voltage Vext to internal voltage Vint according to the output signal from the buffer unit
13
; and a load circuit unit
15
connected between the internal voltage Vint and ground voltage, Vss.
Here, the first current supply unit
12
and the second current supply unit
14
comprise PMOS transistors and the buffer unit
13
comprises two inverter circuits connected in series. The comparison unit
11
comprises difference amplifiers having a current mirror structure for comparing and amplifying reference voltage Vref and internal voltage Vint. The comparison unit
11
inputs reference voltage Vref as an inverting (−) signal and internal voltage Vint as a noninverting (+) signal and then compares their voltage levels to output the resultant signal to node Nd
2
. The first current supply unit
12
supplies current to the load circuit
15
according to the output signal from the comparison unit
11
so that the internal voltage Vint may reach a desired value.
In operation, when internal voltage Vint is lower than the reference voltage Vref, the output node Nd
2
of the comparison unit
11
achieves a ‘low’ signal level, thereby turning on a PMOS transistor P
1
of the first current supply unit
12
and thereby supplying electric current to the load circuit unit
15
. The ‘low’ signal of output node Nd
2
of the comparison unit
11
is buffered through buffer unit
13
, thereby turning on a PMOS transistor P
2
of the second current supply unit
14
and thereby supplying electric current to load circuit unit
15
.
When internal voltage Vint is higher than the reference voltage Vref, output node Nd
2
of the comparison unit
11
achieves a ‘high’ signal level, thereby turning off the PMOS transistor P
1
of the first current supply unit
12
. A ‘high’ signal of the output node Nd
2
turns off the PMOS transistor P
2
of the second current supply unit
14
through the buffer unit
13
, thereby preventing supply of electric current to load circuit unit
15
.
However, the conventional circuit for generating internal power voltage has several drawbacks. For example, in active operation, many current paths are generated in the buffer unit
13
, comprising inverter circuits, since the output signal of the comparison unit
11
is not a digital signal but an analogue signal. As a result, current consumption is increased. Further, when the signal of output node Nd
2
from the comparison unit
11
has an unstable level, a problem arises in that the inverter circuits of the buffer unit
13
do not operate effectively. Here, active operations are operation modes requiring prompt response speed, such as memory read and write in a semiconductor memory device, and regular operations are operation modes in which memory is turned on, such as in a standby state.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made to solve the above problems and an object of the invention is to provide a circuit for generating an internal power voltage capable of reducing consumption power and improving response speed.
In order to achieve the above object, the present invention comprises: a comparison unit for comparing reference voltage and internal voltage; a buffer unit, its input terminal comprising a CMOS inverter, for buffering the output signal of the comparison unit; a buffer control unit for controlling current flowing through the CMOS inverters of the buffer unit within a predetermined amount during regular operation and for controlling current flowing through the CMOS inverters of the buffer unit over the predetermined amount for a restricted time during active operation; a first current supply unit for supplying current according to the output signal of the buffer unit; and a load unit for generating internal voltage by current supplied from the first current supply unit.
It is desirable that a second current supply unit is included in the above structure to supply current to the load unit according to the output signal of the comparison unit. The CMOS inverter of buffer unit comprises PMOS and NMOS supplied with the output signal of the comparison unit through a common gate and obtaining output from a common drain wherein a first PMOS and a second PMOS are connected to the PMOS source of the CMOS inverter and a first NMOS and a second NMOS are connected to the NMOS source of the CMOS inverter. The buffer control unit comprises a constant voltage generating means for supplying constant voltage to gates of the first PMOS and the first NMOS in regular operations of the semiconductor device and a pulse generating means for supplying pulse signals of a predetermined width to gates of the second PMOS and the second NMOS in active operations of the semiconductor device. Here, the semiconductor device is a semiconductor memory device and regular operation indicates the case wherein the semiconductor memory device is turned on and active operation indicates the case wherein read or write operations are performed.
According to the present invention, a circuit for generating internal power voltage of a semiconductor device comprises: a comparison unit for comparing reference voltage Vref and internal voltage Vint; a first current supply unit for supplying external voltage Vext to the internal voltage according to the output signal of the comparison unit; a buffer unit for buffering the output signal of the comparison unit and for outputting the result; a pulse generation unit for increasing the current driving force of the buffer unit during a predetermined time during active operation; a gate bias unit for transforming voltage source supplied to the buffer unit into constant voltage source during other operations; a second current supply unit for supplying the external voltage to internal voltage according to output signal of the buffer unit; and a load circuit unit, connected between the internal voltage and ground voltage, for consuming the internal voltage.
According to the present invention with features as described above, the buffer control unit controls a current flowing through the CMOS inverters of the buffer unit when the voltage is less than a predetermined amount in regular operations. In active operation, the buffer control unit controls the current flowing through the CMOS inverters of the buffer unit when the voltage is more than the predetermined amount and lasts for a predetermined time interval. Therefore, not only is power consumption reduced, both also response speed is shortened when the present invention is used.
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patent: 4451908 (1984-05-01), Takemae et al.
patent: 5136260 (1992-08-01), Yousefi-Elezei
patent: 5349559 (1994-09-01), Park et al.
patent: 5424690 (1995-06-01), Ohno
patent: 5504452 (1996-04-01), Takenaka
patent: 5557571 (1996-09-01), Kato
patent: 5583457 (1996-12-01), Horiguchi et al.
patent: 5710741 (1998-01-01), McLaury
patent: 5717354 (1998-02-01), Kim et al.
patent: 5912855 (1999-06-01), McLaury
patent: 6101142 (2000-08-01), McLaury
patent: 232870 (1999-08-01), None
patent: 029551 (2000-01-01), None
patent: 0243081 (2000-09-01), None
Callahan Timothy P.
Hynix / Semiconductor Inc.
Ladas & Parry
Luu An T.
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