Television – Camera – system and detail – Solid-state image sensor
Reexamination Certificate
2000-05-09
2001-12-11
Ho, Tuan (Department: 2612)
Television
Camera, system and detail
Solid-state image sensor
C348S518000
Reexamination Certificate
active
06330031
ABSTRACT:
FIELD OF INVENTION
The invention relates generally to the field of imaging devices, and more particularly to the synthesis of sample and hold clocks used in correlated double sampling circuits.
BACKGROUND OF THE INVENTION
Semiconductor based imaging has become predominate for conversion of pictorial information into electronic data. Typically, charge coupled devices, CMOS based imagers, and other semiconductor based imagers are used in camcorders, still electronic cameras, fax machines, paper and film scanners.
The output of the semiconductor imager is an analog signal with four distinct “zones” of information. These zones, illustrated in
FIG. 1
, are characterized as reset, back porch, transition and video. The analog output of a semiconductor imager requires a sample and hold circuit to extract a more accurate representation of the video signal. Typically the sample and hold circuit is applied to the analog output of the semiconductor imager, before an analog to digital conversion can be performed. In these circuits the analog output of the semiconductor imager is the input to the sample and hold circuit. This signal is labeled V
in
in FIG.
1
and displays the format of the video signal received from the image sensor. Sample and hold techniques that are applied digitally exist within the prior art. Such a teaching exists within U.S. Pat. 5,086,344 issued to D'Luna et. al, which is commonly assigned with present invention. However, both analog and digital teachings within the prior art discuss voltage level adjustments rather than phase adjustment.
In most systems two sample and holds are used; one to clamp the “back porch” (V
off
) and a second to sample the video (V
sig
). These signals are subtracted to derive a more accurate video signal in what is often called Correlated Double Sampling (CDS). A larger magnitude difference indicates that more light has been detected.
A reset signal is used by the output stage of the imager to dump the charge associated with the previous output. This reset signal is capacitively coupled to the video output and typically leaves an artifact in the form of a positive pulse. For a CCD this pulse would be on the order of 100-600mV (V
rst
). The rising edge of this pulse terminates the current output and the falling edge starts the next output.
Current art uses a single timing generator to create the reset, clamp and sample signals with the correct phase relationship to the analog video signal. There are timing requirements for minimum sample to reset delays, and reset to clamp delays. The system tolerance is typically added to these delays to guarantee that these requirements are met. This cumulative timing requirement typically results in a reduction of duty cycle for the clamp and sample pulses. Smaller pulses make it more difficult for the sample and holds to acquire the signals.
A typical system would have four separate ICs. If the propagation delay through each chip was known, the system could be designed to generate the proper phase relationship between the CDS pulses and the analog video. The problem is that the propagation delay is not constant between batches of chips, or over time and temperature.
The majority of the timing uncertainty occurs at the interfaces between chips. Each chip crossing might contribute a 5ns uncertainty. For three chip crossings, this would correspond to a total of 15ns worst case skew between the clamp sample pulses and the analog video. In fast systems the skew may be a significant portion of the total timing budget. At a pixel output rate of 20mhz, the sample window (T
sa
) would be 50ns/4 or 12.5ns. If the system skew were 15ns, it would be impossible to build the system with the ability to properly adjust the signal delays in the system.
Tapped analog or digital delay lines could be used to delay the analog V
in
or the digital clamp and sample pulses in the system. However, these delay line based systems require that various levels of calibration be performed. The level of calibration could easily vary and the calibration process would increase manufacturing cost and would not necessarily adapt to system variations resulting from temperature fluctuations and the aging process of the system.
If the sample pulse is not in the correct phase with the analog V
in
, the sample and hold will acquire the signal on a sloping zone of V
in
making the video signal extremely sensitive to clock jitter. Delay errors can greatly decrease the signal amplitude and make the system non-linear.
It should be apparent from the foregoing discussion that there remains a need in the art for devices and methods that will apply sample pulses to imager output signals in a manner that maintains proper phase relationships. This and other shortcomings within the prior art are addressed by the teachings of the present invention.
SUMMARY OF THE INVENTION
The present invention is directed to overcoming one or more of the problems set forth above. Briefly summarized, according to one aspect of the present invention, by identifying the artifact of the reset signal from the output of the semiconductor imager, V
in
, which is input into a correlated double sampling unit, CDS, it is possible to create sample and clamp clock signals that have the ideal phase relationship to V
in
. The identified reset pulse is then used to synthesize the CDS clocks or to modify existing CDS clocks.
By implementing this reset signal identification and CDS clock generation on the same integrated circuit, all chip crossings associated with tolerance build up are removed. This has the added benefit of reducing by two the required number of interface pins between the CDS and the timing generator, potentially reducing package costs.
These and other aspects, objects, features and advantages of the present invention will be more clearly understood and appreciated from a review of the following detailed description of the preferred embodiments and appended claims, and by reference to the accompanying drawings.
ADVANTAGEOUS EFFECT OF THE INVENTION
The present invention has the following advantages over the prior art: (1) it minimizes tolerance buildup on timing of the CDS clocks which results in easing system timing requirements; (2) it reduces the number of pins required to interface the timing generator to CDS by two pins; (3) it maximizes the video signal level by generating more accurate CDS clocks which results in higher speed operation; and (4) allows for wider clamp and sample clocks due to the minimized skew that is provided for by the present invention.
REFERENCES:
patent: 4831444 (1989-05-01), Kato
patent: 5144444 (1992-09-01), MacLean
patent: 5696553 (1997-12-01), D'Alfonso et al.
Eastman Kodak Company
Ho Tuan
Watkins Peyton C.
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