Pulse or digital communications – Synchronizers
Reexamination Certificate
2006-01-24
2006-01-24
Corrielus, Jean B. (Department: 2637)
Pulse or digital communications
Synchronizers
C375S376000, C327S141000, C370S503000
Reexamination Certificate
active
06990159
ABSTRACT:
A circuit arrangement for a communication system for terminating a plurality of interfaces at a common bus and for generating a synchronization clock for synchronizing the bus is provided. In one aspect, a circuit arrangement for a communication system includes a first multiplexer controlled by a first control signal with a plurality of inputs corresponding to a plurality of transmission lines of the interfaces, a respective phase control unit, preceding each input of the first multiplexer, which derives a respective clock generator signal from a received signal of the corresponding transmission line, where the clock generator signal of one of the transmission lines is switched through as output signal of the first multiplexer in dependence on the first control signal, and a phase locked loop, at the inputs of which the output signal of the first multiplexer and a clock from a clock generator operated with an external crystal oscillator.
REFERENCES:
patent: 6127858 (2000-10-01), Stinson et al.
patent: 6433645 (2002-08-01), Mann et al.
patent: 6687320 (2004-02-01), Chiu et al.
Balb Markus
Fiessinger Walter
Schedel Ralf
Corrielus Jean B.
Maginot Moore & Beck
LandOfFree
Circuit for generating clock pulses in a communications system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit for generating clock pulses in a communications system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit for generating clock pulses in a communications system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3549080