Circuit for generating a stretched clock signal by one period or

Details Circuit for generating a stretched clock signal by one period or Circuit for generating a stretched clock signal by one period or

1992-04-17

1994-05-17

Sikes, William L.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307269, 328 58, H03K 504

Patent

active

053131088

ABSTRACT:
The time a microprocessor CPU must wait for memory access is controlled to be one of two values by stretching the CPU clock signal either a first time duration or a second time duration, depending on the expected delay caused by the memory access. The clock stretching is in increments of one quarter of the CPU clock period and is done with both the leading and trailing edges of the clock pulse.

REFERENCES:
patent: 4105978 (1978-08-01), Goss et al.
patent: 4355283 (1982-10-01), Ott
patent: 4636656 (1987-01-01), Snowden et al.
patent: 4862096 (1989-08-01), Spence
patent: 5045715 (1991-09-01), Fitch

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