Circuit for generating a clock signal which is locked to a speci

Details Circuit for generating a clock signal which is locked to a speci Circuit for generating a clock signal which is locked to a speci

1991-08-09

1993-09-07

Groody, James J.

Facsimile and static presentation processing

Static presentation processing

Attribute control

358 20, H04N 966

Patent

active

052434125

ABSTRACT:
A sampling clock signal, which determines sampling time points in an A/D converter used to convert a color video signal to digital form, is locked to a specific predetermined phase of the color burst signal of the video signal, by a negative feedback loop formed of a circuit for deriving successive color burst phase values from the digital color signal values, a gate circuit and a subtractor for obtaining the difference between color burst phase and a reference phase value, for one specific A/D conversion sampling time point in each horizontal scanning interval, and circuits for producing the sampling clock signal and controlling the phase of that signal in accordance with the phase difference values.

REFERENCES:
patent: 4291332 (1981-09-01), Kato et al.
patent: 4527145 (1985-07-01), Haussmann et al.
Jul., 1988 edition of the magazine "Electronics" published in Japan, pp. 47-53.

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