Circuit for freezing the data in an interface buffer

Details Circuit for freezing the data in an interface buffer Circuit for freezing the data in an interface buffer

1995-02-03

1996-07-30

Chin, Wellington

Multiplex communications

Wide area network

Packet switching

370 851, H04L 1240

Patent

active

055419321

ABSTRACT:
A circuit for enabling data transfer between one data bus connected to a number of devices, such as accelerator cards, and a second data bus, such as one found in a computer. The two data busses are connected by a number of FIFO buffers, and an arbitrator selects a source and destination for each packet. The circuit allows the computer to freeze the data in any or all buffers so that it can be inspected and changed if necessary, but only after the entire current packet for the selected buffer or buffers has been transferred.

REFERENCES:
patent: 5029124 (1991-07-01), Leahy et al.
patent: 5191581 (1993-03-01), Woodbury et al.

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