Circuit for fast and accurate memory read operations

Details Circuit for fast and accurate memory read operations Circuit for fast and accurate memory read operations

2003-03-13

2004-06-01

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185160, C365S185180

Reexamination Certificate

active

06744674

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to the field of semiconductor devices. More particularly, the present invention relates to semiconductor memory devices.
BACKGROUND ART
Memory devices are known in the art for storing data in a wide variety of electronic devices and applications. A typical memory device comprises a number of memory cells. Often, memory cells are arranged in an array format, where a row of memory cells corresponds to a word line and a column of memory cells corresponds to a bit line, and where each memory cell defines a binary bit, i.e., either a zero (“0”) bit or a one (“1”) bit. For example, a memory cell may be defined as either being a “programmed” cell or an “erased” cell. According to one particular convention, a programmed cell is representative of a “0” bit, and an erased cell is representative of a “1” bit. In one type of memory cell, each cell stores two binary bits, a “left bit” and a “right bit.” The left bit can represent a “0” or a “1” while the right bit can represent a “0” or a “1” independent of the left bit.
Typically, the state of a memory cell is determined during a read operation by sensing the current drawn by the memory cell. For example, to ascertain the current drawn by a particular memory cell using drain-side sensing, the drain terminal of the memory cell is connected to a sensing circuit, the source terminal of the memory cell is connected to ground, and the gate of the memory cell is selected. The sensing circuit attempts to detect the current drawn by the memory cell, and compares the sensed memory cell current against a reference current. If the sensed memory cell current exceeds the reference current, the memory cell is considered an erased cell (corresponding to a “1” bit). However, if the sensed memory cell current is below the reference current, the memory cell is considered a programmed cell (corresponding to a “0” bit).
In practice, it is desirable to have the sensed memory cell current be greater than or less than the reference current by a “read margin.” In the present application, read margin is defined as the absolute value of the difference between current drawn by a target memory cell and the current drawn by a reference cell during a read operation. With a sufficient read margin, the impact of extraneous factors, such as noise, for example, upon the detection of the memory cell current is greatly reduced. By way of illustration, suppose the reference current used for comparison is fifteen (15) microAmps (&mgr;A) in a particular memory device. In this case, in order to provide a read margin of five (5) &mgr;A, it would be desirable to sense a memory cell current of twenty (20) &mgr;A or greater for an erased cell (corresponding to a “1” bit) and a memory cell current of ten (10) &mgr;A or less for a programmed cell (corresponding to a “0” bit). With a 5 &mgr;A read margin, the impact of extraneous factors, such as noise, is significantly reduced.
Conventional memory circuits, however, considerably reduce the read margin for sensing memory cell current during read operations (in the present application, reduction of the read margin is also referred to as “read margin loss”). When the read margin is significantly reduced, the reliability of sensing the memory cell current also decreases, since extraneous factors, such as noise, have a greater impact. The reliability and accuracy of the read operation are thus reduced, resulting in poor performance of the memory device. Accordingly, there exists a strong need in the art to overcome deficiencies of known memory circuits and to provide a memory circuit and technique which results in reduced read margin loss in a fast and accurate manner during memory read operations.
SUMMARY
The present invention is directed to a circuit for fast and accurate memory read operations. The invention addresses and resolves the need in the art for a memory circuit and technique which results in reduced read margin loss in a fast and accurate manner during memory read operations. According to one exemplary embodiment, the memory circuit for sensing current in a target cell during a read operation comprises the target cell, a first neighboring cell, and an operational amplifier. In the exemplary embodiment, the target cell has a first bit line connected to ground, and further has a second bit line connected to a drain voltage. A sensing circuit is coupled at a first node to at least one of the first bit line or the second bit line. For example, in drain-side sensing, the sensing circuit is coupled to the second bit line whereas in source-side sensing, the sensing circuit is coupled to the first bit line. The first neighboring cell has a third bit line connected to a second node. The operational amplifier has an output terminal connected at the second node to the third bit line. The operational amplifier also has a noninverting input terminal connected to said first node, and has an inverting input terminal connected to the second node. Each of the target cell and the first neighboring cell comprises a respective gate terminal connected to a common word line. In some embodiments, the target cell may also store a first bit and a second bit.
According to another exemplary embodiment, the memory circuit further comprises a second neighboring cell and a third neighboring cell. In this particular embodiment, the second neighboring cell has a fourth bit line coupled to the first node, and the second neighboring cell is adjacent to the target cell. The third neighboring cell also has a fifth bit line coupled to the first node. The third neighboring cell is adjacent to the second neighboring cell, and the first neighboring cell is adjacent to the third neighboring cell. According to another exemplary embodiment, the memory circuit further comprises a fourth neighboring cell. In this particular embodiment, the fourth neighboring cell has a sixth bit line coupled to the second node, and the fourth neighboring cell is adjacent to the first neighboring cell. According to yet another exemplary embodiment, the memory circuit further comprises a fifth neighboring cell. In this particular embodiment, the fifth neighboring cell has a seventh bit line coupled to the second node, and the fifth neighboring cell is adjacent to the fourth neighboring cell.


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